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| author | Ye.Li <B37916@freescale.com> | 2015-03-02 21:06:23 +0800 |
|---|---|---|
| committer | Peng Fan <Peng.Fan@freescale.com> | 2015-04-29 15:00:32 +0800 |
| commit | bac2fceb67056eca6a6a3e85cac5aa90a73624b8 (patch) | |
| tree | b2c918658ceac4ab762a61f1e6564aa174e3146c /arch/arm/cpu | |
| parent | eefcd91b30a0ee7ae2f0f3d03d4f4e667374443b (diff) | |
| download | u-boot-imx-bac2fceb67056eca6a6a3e85cac5aa90a73624b8.zip u-boot-imx-bac2fceb67056eca6a6a3e85cac5aa90a73624b8.tar.gz u-boot-imx-bac2fceb67056eca6a6a3e85cac5aa90a73624b8.tar.bz2 | |
MLK-10363-1 udc: Update i.MX udc driver to support MX7
Update driver codes and registers define for MX7. Implement udc callback
function in MX7 arch.
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit e55c4f7bf5a66b34c2d01c42bac667cb3789b0c1)
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Diffstat (limited to 'arch/arm/cpu')
| -rw-r--r-- | arch/arm/cpu/armv7/mx7/soc.c | 26 |
1 files changed, 2 insertions, 24 deletions
diff --git a/arch/arm/cpu/armv7/mx7/soc.c b/arch/arm/cpu/armv7/mx7/soc.c index a9e351f..d737f96 100644 --- a/arch/arm/cpu/armv7/mx7/soc.c +++ b/arch/arm/cpu/armv7/mx7/soc.c @@ -22,10 +22,6 @@ #include <recovery.h> #endif #endif -#ifdef CONFIG_IMX_UDC -#include <asm/arch/mx7_usbphy.h> -#include <usb/imx_udc.h> -#endif struct src *src_reg = (struct src *)SRC_BASE_ADDR; @@ -412,30 +408,12 @@ void set_usb_phy1_clk(void) } void enable_usb_phy1_clk(unsigned char enable) { - if (enable) - writel(BM_USBPHY_CTRL_CLKGATE, - USB_PHY0_BASE_ADDR + HW_USBPHY_CTRL_CLR); - else - writel(BM_USBPHY_CTRL_CLKGATE, - USB_PHY0_BASE_ADDR + HW_USBPHY_CTRL_SET); } void reset_usb_phy1(void) { /* Reset USBPHY module */ - u32 temp; - temp = readl(USB_PHY0_BASE_ADDR + HW_USBPHY_CTRL); - temp |= BM_USBPHY_CTRL_SFTRST; - writel(temp, USB_PHY0_BASE_ADDR + HW_USBPHY_CTRL); - udelay(10); - - /* Remove CLKGATE and SFTRST */ - temp = readl(USB_PHY0_BASE_ADDR + HW_USBPHY_CTRL); - temp &= ~(BM_USBPHY_CTRL_CLKGATE | BM_USBPHY_CTRL_SFTRST); - writel(temp, USB_PHY0_BASE_ADDR + HW_USBPHY_CTRL); - udelay(10); - - /* Power up the PHY */ - writel(0, USB_PHY0_BASE_ADDR + HW_USBPHY_PWD); + setbits_le32(&src_reg->usbophy1_rcr, 0x00000001); } + #endif |