diff options
author | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2015-04-10 14:22:23 +0200 |
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committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2015-04-10 14:22:23 +0200 |
commit | b491d9757d14415edcb1468ed896a704d0f0cfe7 (patch) | |
tree | 477707170048989accc9ea69cd6ac5edae7b1aec /arch/arm/cpu | |
parent | 79d75d752717fb4106ec49abaddbd7744c775a35 (diff) | |
parent | 385a08a60f042061b004642d6b9bb6cfb794ad5a (diff) | |
download | u-boot-imx-b491d9757d14415edcb1468ed896a704d0f0cfe7.zip u-boot-imx-b491d9757d14415edcb1468ed896a704d0f0cfe7.tar.gz u-boot-imx-b491d9757d14415edcb1468ed896a704d0f0cfe7.tar.bz2 |
Merge branch 'u-boot/master'
Diffstat (limited to 'arch/arm/cpu')
-rw-r--r-- | arch/arm/cpu/arm1176/Makefile | 2 | ||||
-rw-r--r-- | arch/arm/cpu/arm1176/bcm2835/Kconfig | 12 | ||||
-rw-r--r-- | arch/arm/cpu/arm1176/bcm2835/Makefile | 8 | ||||
-rw-r--r-- | arch/arm/cpu/arm1176/bcm2835/init.c | 24 | ||||
-rw-r--r-- | arch/arm/cpu/arm1176/bcm2835/lowlevel_init.S | 19 | ||||
-rw-r--r-- | arch/arm/cpu/arm1176/bcm2835/mbox.c | 153 | ||||
-rw-r--r-- | arch/arm/cpu/arm1176/bcm2835/reset.c | 35 | ||||
-rw-r--r-- | arch/arm/cpu/arm1176/bcm2835/timer.c | 58 | ||||
-rw-r--r-- | arch/arm/cpu/armv7/Makefile | 1 | ||||
-rw-r--r-- | arch/arm/cpu/armv7/am33xx/ddr.c | 2 | ||||
-rw-r--r-- | arch/arm/cpu/armv7/bcm2835/Makefile | 13 | ||||
-rw-r--r-- | arch/arm/cpu/armv7/exynos/Kconfig | 6 | ||||
-rw-r--r-- | arch/arm/cpu/armv7/exynos/clock.c | 69 | ||||
-rw-r--r-- | arch/arm/cpu/armv7/exynos/clock_init_exynos5.c | 4 | ||||
-rw-r--r-- | arch/arm/cpu/armv7/mx6/Kconfig | 42 | ||||
-rw-r--r-- | arch/arm/cpu/armv7/omap3/Kconfig | 6 | ||||
-rw-r--r-- | arch/arm/cpu/armv7/sunxi/clock_sun4i.c | 35 | ||||
-rw-r--r-- | arch/arm/cpu/armv7/sunxi/psci.S | 2 | ||||
-rw-r--r-- | arch/arm/cpu/armv7/sunxi/usbc.c | 7 | ||||
-rw-r--r-- | arch/arm/cpu/tegra210-common/pinmux.c | 195 |
20 files changed, 136 insertions, 557 deletions
diff --git a/arch/arm/cpu/arm1176/Makefile b/arch/arm/cpu/arm1176/Makefile index 480e130..deec427 100644 --- a/arch/arm/cpu/arm1176/Makefile +++ b/arch/arm/cpu/arm1176/Makefile @@ -10,5 +10,3 @@ extra-y = start.o obj-y = cpu.o - -obj-$(CONFIG_BCM2835) += bcm2835/ diff --git a/arch/arm/cpu/arm1176/bcm2835/Kconfig b/arch/arm/cpu/arm1176/bcm2835/Kconfig deleted file mode 100644 index 73cc72b..0000000 --- a/arch/arm/cpu/arm1176/bcm2835/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_RPI || TARGET_RPI_2 - -config DM - default y - -config DM_SERIAL - default y - -config DM_GPIO - default y - -endif diff --git a/arch/arm/cpu/arm1176/bcm2835/Makefile b/arch/arm/cpu/arm1176/bcm2835/Makefile deleted file mode 100644 index 7e5dbe1..0000000 --- a/arch/arm/cpu/arm1176/bcm2835/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2012 Stephen Warren -# -# SPDX-License-Identifier: GPL-2.0 -# - -obj-y := lowlevel_init.o -obj-y += init.o reset.o timer.o mbox.o diff --git a/arch/arm/cpu/arm1176/bcm2835/init.c b/arch/arm/cpu/arm1176/bcm2835/init.c deleted file mode 100644 index e90d3bb..0000000 --- a/arch/arm/cpu/arm1176/bcm2835/init.c +++ /dev/null @@ -1,24 +0,0 @@ -/* - * (C) Copyright 2012 Stephen Warren - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <common.h> - -int arch_cpu_init(void) -{ - icache_enable(); - - return 0; -} diff --git a/arch/arm/cpu/arm1176/bcm2835/lowlevel_init.S b/arch/arm/cpu/arm1176/bcm2835/lowlevel_init.S deleted file mode 100644 index c7b0843..0000000 --- a/arch/arm/cpu/arm1176/bcm2835/lowlevel_init.S +++ /dev/null @@ -1,19 +0,0 @@ -/* - * (C) Copyright 2012 Stephen Warren - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -.globl lowlevel_init -lowlevel_init: - mov pc, lr diff --git a/arch/arm/cpu/arm1176/bcm2835/mbox.c b/arch/arm/cpu/arm1176/bcm2835/mbox.c deleted file mode 100644 index 3b17a31..0000000 --- a/arch/arm/cpu/arm1176/bcm2835/mbox.c +++ /dev/null @@ -1,153 +0,0 @@ -/* - * (C) Copyright 2012 Stephen Warren - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/mbox.h> - -#define TIMEOUT 1000 /* ms */ - -int bcm2835_mbox_call_raw(u32 chan, u32 send, u32 *recv) -{ - struct bcm2835_mbox_regs *regs = - (struct bcm2835_mbox_regs *)BCM2835_MBOX_PHYSADDR; - ulong endtime = get_timer(0) + TIMEOUT; - u32 val; - - debug("time: %lu timeout: %lu\n", get_timer(0), endtime); - - if (send & BCM2835_CHAN_MASK) { - printf("mbox: Illegal mbox data 0x%08x\n", send); - return -1; - } - - /* Drain any stale responses */ - - for (;;) { - val = readl(®s->status); - if (val & BCM2835_MBOX_STATUS_RD_EMPTY) - break; - if (get_timer(0) >= endtime) { - printf("mbox: Timeout draining stale responses\n"); - return -1; - } - val = readl(®s->read); - } - - /* Wait for space to send */ - - for (;;) { - val = readl(®s->status); - if (!(val & BCM2835_MBOX_STATUS_WR_FULL)) - break; - if (get_timer(0) >= endtime) { - printf("mbox: Timeout waiting for send space\n"); - return -1; - } - } - - /* Send the request */ - - val = BCM2835_MBOX_PACK(chan, send); - debug("mbox: TX raw: 0x%08x\n", val); - writel(val, ®s->write); - - /* Wait for the response */ - - for (;;) { - val = readl(®s->status); - if (!(val & BCM2835_MBOX_STATUS_RD_EMPTY)) - break; - if (get_timer(0) >= endtime) { - printf("mbox: Timeout waiting for response\n"); - return -1; - } - } - - /* Read the response */ - - val = readl(®s->read); - debug("mbox: RX raw: 0x%08x\n", val); - - /* Validate the response */ - - if (BCM2835_MBOX_UNPACK_CHAN(val) != chan) { - printf("mbox: Response channel mismatch\n"); - return -1; - } - - *recv = BCM2835_MBOX_UNPACK_DATA(val); - - return 0; -} - -#ifdef DEBUG -void dump_buf(struct bcm2835_mbox_hdr *buffer) -{ - u32 *p; - u32 words; - int i; - - p = (u32 *)buffer; - words = buffer->buf_size / 4; - for (i = 0; i < words; i++) - printf(" 0x%04x: 0x%08x\n", i * 4, p[i]); -} -#endif - -int bcm2835_mbox_call_prop(u32 chan, struct bcm2835_mbox_hdr *buffer) -{ - int ret; - u32 rbuffer; - struct bcm2835_mbox_tag_hdr *tag; - int tag_index; - -#ifdef DEBUG - printf("mbox: TX buffer\n"); - dump_buf(buffer); -#endif - - ret = bcm2835_mbox_call_raw(chan, (u32)buffer, &rbuffer); - if (ret) - return ret; - if (rbuffer != (u32)buffer) { - printf("mbox: Response buffer mismatch\n"); - return -1; - } - -#ifdef DEBUG - printf("mbox: RX buffer\n"); - dump_buf(buffer); -#endif - - /* Validate overall response status */ - - if (buffer->code != BCM2835_MBOX_RESP_CODE_SUCCESS) { - printf("mbox: Header response code invalid\n"); - return -1; - } - - /* Validate each tag's response status */ - - tag = (void *)(buffer + 1); - tag_index = 0; - while (tag->tag) { - if (!(tag->val_len & BCM2835_MBOX_TAG_VAL_LEN_RESPONSE)) { - printf("mbox: Tag %d missing val_len response bit\n", - tag_index); - return -1; - } - /* - * Clear the reponse bit so clients can just look right at the - * length field without extra processing - */ - tag->val_len &= ~BCM2835_MBOX_TAG_VAL_LEN_RESPONSE; - tag = (void *)(((u8 *)tag) + sizeof(*tag) + tag->val_buf_size); - tag_index++; - } - - return 0; -} diff --git a/arch/arm/cpu/arm1176/bcm2835/reset.c b/arch/arm/cpu/arm1176/bcm2835/reset.c deleted file mode 100644 index 8c37ad9..0000000 --- a/arch/arm/cpu/arm1176/bcm2835/reset.c +++ /dev/null @@ -1,35 +0,0 @@ -/* - * (C) Copyright 2012 Stephen Warren - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/wdog.h> - -#define RESET_TIMEOUT 10 - -void reset_cpu(ulong addr) -{ - struct bcm2835_wdog_regs *regs = - (struct bcm2835_wdog_regs *)BCM2835_WDOG_PHYSADDR; - uint32_t rstc; - - rstc = readl(®s->rstc); - rstc &= ~BCM2835_WDOG_RSTC_WRCFG_MASK; - rstc |= BCM2835_WDOG_RSTC_WRCFG_FULL_RESET; - - writel(BCM2835_WDOG_PASSWORD | RESET_TIMEOUT, ®s->wdog); - writel(BCM2835_WDOG_PASSWORD | rstc, ®s->rstc); -} diff --git a/arch/arm/cpu/arm1176/bcm2835/timer.c b/arch/arm/cpu/arm1176/bcm2835/timer.c deleted file mode 100644 index 017907c..0000000 --- a/arch/arm/cpu/arm1176/bcm2835/timer.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - * (C) Copyright 2012 Stephen Warren - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/timer.h> - -ulong get_timer_us(ulong base) -{ - struct bcm2835_timer_regs *regs = - (struct bcm2835_timer_regs *)BCM2835_TIMER_PHYSADDR; - - return readl(®s->clo) - base; -} - -ulong get_timer(ulong base) -{ - ulong us = get_timer_us(0); - us /= (1000000 / CONFIG_SYS_HZ); - us -= base; - return us; -} - -unsigned long long get_ticks(void) -{ - return get_timer(0); -} - -ulong get_tbclk(void) -{ - return CONFIG_SYS_HZ; -} - -void __udelay(unsigned long usec) -{ - ulong endtime; - signed long diff; - - endtime = get_timer_us(0) + usec; - - do { - ulong now = get_timer_us(0); - diff = endtime - now; - } while (diff >= 0); -} diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index 1312a9d..21fc03b 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -39,7 +39,6 @@ endif obj-$(if $(filter am33xx,$(SOC)),y) += am33xx/ obj-$(if $(filter armada-xp,$(SOC)),y) += armada-xp/ -obj-$(CONFIG_BCM2835) += bcm2835/ obj-$(if $(filter bcm281xx,$(SOC)),y) += bcm281xx/ obj-$(if $(filter bcmcygnus,$(SOC)),y) += bcmcygnus/ obj-$(if $(filter bcmnsp,$(SOC)),y) += bcmnsp/ diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c index 85cceae..f5b16b4 100644 --- a/arch/arm/cpu/armv7/am33xx/ddr.c +++ b/arch/arm/cpu/armv7/am33xx/ddr.c @@ -164,9 +164,9 @@ void config_sdram(const struct emif_regs *regs, int nr) writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl); writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw); } - writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config); writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl); writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw); + writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config); } /** diff --git a/arch/arm/cpu/armv7/bcm2835/Makefile b/arch/arm/cpu/armv7/bcm2835/Makefile deleted file mode 100644 index ed1ee47..0000000 --- a/arch/arm/cpu/armv7/bcm2835/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -# -# (C) Copyright 2012 Stephen Warren -# -# SPDX-License-Identifier: GPL-2.0+ -# - -src_dir := ../../arm1176/bcm2835/ - -obj-y := -obj-y += $(src_dir)/init.o -obj-y += $(src_dir)/reset.o -obj-y += $(src_dir)/timer.o -obj-y += $(src_dir)/mbox.o diff --git a/arch/arm/cpu/armv7/exynos/Kconfig b/arch/arm/cpu/armv7/exynos/Kconfig index eb86a7f..bd7540a 100644 --- a/arch/arm/cpu/armv7/exynos/Kconfig +++ b/arch/arm/cpu/armv7/exynos/Kconfig @@ -80,12 +80,6 @@ config DM_SPI_FLASH config DM_GPIO default y -config SYS_MALLOC_F - default y - -config SYS_MALLOC_F_LEN - default 0x400 - source "board/samsung/smdkv310/Kconfig" source "board/samsung/trats/Kconfig" source "board/samsung/universal_c210/Kconfig" diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index c6455c2..df4d473 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -14,7 +14,6 @@ #define PLL_DIV_1024 1024 #define PLL_DIV_65535 65535 #define PLL_DIV_65536 65536 - /* * * This structure is to store the src bit, div bit and prediv bit * positions of the peripheral clocks of the src and div registers @@ -423,8 +422,8 @@ static unsigned long exynos5_get_periph_rate(int peripheral) case PERIPH_ID_I2C6: case PERIPH_ID_I2C7: src = EXYNOS_SRC_MPLL; - div = readl(&clk->div_top0); - sub_div = readl(&clk->div_top1); + div = readl(&clk->div_top1); + sub_div = readl(&clk->div_top0); break; default: debug("%s: invalid peripheral %d", __func__, peripheral); @@ -1028,6 +1027,40 @@ static unsigned long exynos5420_get_lcd_clk(void) return pclk; } +static unsigned long exynos5800_get_lcd_clk(void) +{ + struct exynos5420_clock *clk = + (struct exynos5420_clock *)samsung_get_base_clock(); + unsigned long sclk; + unsigned int sel; + unsigned int ratio; + + /* + * CLK_SRC_DISP10 + * CLKMUX_FIMD1 [6:4] + */ + sel = (readl(&clk->src_disp10) >> 4) & 0x7; + + if (sel) { + /* + * Mapping of CLK_SRC_DISP10 CLKMUX_FIMD1 [6:4] values into + * PLLs. The first element is a placeholder to bypass the + * default settig. + */ + const int reg_map[] = {0, CPLL, DPLL, MPLL, SPLL, IPLL, EPLL, + RPLL}; + sclk = get_pll_clk(reg_map[sel]); + } else + sclk = CONFIG_SYS_CLK_FREQ; + /* + * CLK_DIV_DISP10 + * FIMD1_RATIO [3:0] + */ + ratio = readl(&clk->div_disp10) & 0xf; + + return sclk / (ratio + 1); +} + void exynos4_set_lcd_clk(void) { struct exynos4_clock *clk = @@ -1159,6 +1192,28 @@ void exynos5420_set_lcd_clk(void) writel(cfg, &clk->div_disp10); } +void exynos5800_set_lcd_clk(void) +{ + struct exynos5420_clock *clk = + (struct exynos5420_clock *)samsung_get_base_clock(); + unsigned int cfg; + + /* + * Use RPLL for pixel clock + * CLK_SRC_DISP10 CLKMUX_FIMD1 [6:4] + * ================== + * 111: SCLK_RPLL + */ + cfg = readl(&clk->src_disp10) | (0x7 << 4); + writel(cfg, &clk->src_disp10); + + /* + * CLK_DIV_DISP10 + * FIMD1_RATIO [3:0] + */ + clrsetbits_le32(&clk->div_disp10, 0xf << 0, 0x0 << 0); +} + void exynos4_set_mipi_clk(void) { struct exynos4_clock *clk = @@ -1646,8 +1701,10 @@ unsigned long get_lcd_clk(void) if (cpu_is_exynos4()) return exynos4_get_lcd_clk(); else { - if (proid_is_exynos5420() || proid_is_exynos5800()) + if (proid_is_exynos5420()) return exynos5420_get_lcd_clk(); + else if (proid_is_exynos5800()) + return exynos5800_get_lcd_clk(); else return exynos5_get_lcd_clk(); } @@ -1660,8 +1717,10 @@ void set_lcd_clk(void) else { if (proid_is_exynos5250()) exynos5_set_lcd_clk(); - else if (proid_is_exynos5420() || proid_is_exynos5800()) + else if (proid_is_exynos5420()) exynos5420_set_lcd_clk(); + else + exynos5800_set_lcd_clk(); } } diff --git a/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c index 0aff3d0..0200fd1 100644 --- a/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c +++ b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c @@ -179,10 +179,10 @@ struct mem_timings mem_timings[] = { .spll_mdiv = 0xc8, .spll_pdiv = 0x3, .spll_sdiv = 0x2, - /* RPLL @70.5Mhz */ + /* RPLL @141Mhz */ .rpll_mdiv = 0x5E, .rpll_pdiv = 0x2, - .rpll_sdiv = 0x4, + .rpll_sdiv = 0x3, .direct_cmd_msr = { 0x00020018, 0x00030000, 0x00010046, 0x00000d70, diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig new file mode 100644 index 0000000..076ba52 --- /dev/null +++ b/arch/arm/cpu/armv7/mx6/Kconfig @@ -0,0 +1,42 @@ +if ARCH_MX6 + +config MX6 + bool + default y + +config MX6D + bool + +config MX6DL + bool + +config MX6Q + bool + +config MX6QDL + bool + +config MX6S + bool + +config MX6SL + bool + +config MX6SX + bool + +choice + prompt "MX6 board select" + +config TARGET_SECOMX6 + bool "Support secomx6 boards" + select CPU_V7 + +endchoice + +config SYS_SOC + default "mx6" + +source "board/seco/Kconfig" + +endif diff --git a/arch/arm/cpu/armv7/omap3/Kconfig b/arch/arm/cpu/armv7/omap3/Kconfig index 65da6e2..1f96498 100644 --- a/arch/arm/cpu/armv7/omap3/Kconfig +++ b/arch/arm/cpu/armv7/omap3/Kconfig @@ -106,12 +106,6 @@ config DM_GPIO config DM_SERIAL default y if DM -config SYS_MALLOC_F - default y if DM - -config SYS_MALLOC_F_LEN - default 0x400 if DM - config SYS_SOC default "omap3" diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c index 49f4032..c3e04af 100644 --- a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c +++ b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c @@ -100,22 +100,23 @@ static struct { unsigned int freq; } pll1_para[] = { /* This array must be ordered by frequency. */ - { PLL1_CFG(16, 0, 0, 0), 384000000 }, - { PLL1_CFG(16, 1, 0, 0), 768000000 }, - { PLL1_CFG(20, 1, 0, 0), 960000000 }, - { PLL1_CFG(21, 1, 0, 0), 1008000000}, - { PLL1_CFG(22, 1, 0, 0), 1056000000}, - { PLL1_CFG(23, 1, 0, 0), 1104000000}, - { PLL1_CFG(24, 1, 0, 0), 1152000000}, - { PLL1_CFG(25, 1, 0, 0), 1200000000}, - { PLL1_CFG(26, 1, 0, 0), 1248000000}, - { PLL1_CFG(27, 1, 0, 0), 1296000000}, - { PLL1_CFG(28, 1, 0, 0), 1344000000}, - { PLL1_CFG(29, 1, 0, 0), 1392000000}, - { PLL1_CFG(30, 1, 0, 0), 1440000000}, { PLL1_CFG(31, 1, 0, 0), 1488000000}, - /* Final catchall entry */ - { PLL1_CFG(31, 1, 0, 0), ~0}, + { PLL1_CFG(30, 1, 0, 0), 1440000000}, + { PLL1_CFG(29, 1, 0, 0), 1392000000}, + { PLL1_CFG(28, 1, 0, 0), 1344000000}, + { PLL1_CFG(27, 1, 0, 0), 1296000000}, + { PLL1_CFG(26, 1, 0, 0), 1248000000}, + { PLL1_CFG(25, 1, 0, 0), 1200000000}, + { PLL1_CFG(24, 1, 0, 0), 1152000000}, + { PLL1_CFG(23, 1, 0, 0), 1104000000}, + { PLL1_CFG(22, 1, 0, 0), 1056000000}, + { PLL1_CFG(21, 1, 0, 0), 1008000000}, + { PLL1_CFG(20, 1, 0, 0), 960000000 }, + { PLL1_CFG(19, 1, 0, 0), 912000000 }, + { PLL1_CFG(16, 1, 0, 0), 768000000 }, + /* Final catchall entry 384MHz*/ + { PLL1_CFG(16, 0, 0, 0), 0 }, + }; void clock_set_pll1(unsigned int hz) @@ -126,10 +127,12 @@ void clock_set_pll1(unsigned int hz) (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; /* Find target frequency */ - while (pll1_para[i].freq < hz) + while (pll1_para[i].freq > hz) i++; hz = pll1_para[i].freq; + if (! hz) + hz = 384000000; /* Calculate system clock divisors */ axi = DIV_ROUND_UP(hz, 432000000); /* Max 450MHz */ diff --git a/arch/arm/cpu/armv7/sunxi/psci.S b/arch/arm/cpu/armv7/sunxi/psci.S index 5be497b..e0a524e 100644 --- a/arch/arm/cpu/armv7/sunxi/psci.S +++ b/arch/arm/cpu/armv7/sunxi/psci.S @@ -37,7 +37,7 @@ .arch_extension sec -#define ONE_MS (CONFIG_SYS_CLK_FREQ / 1000) +#define ONE_MS (CONFIG_TIMER_CLK_FREQ / 1000) #define TEN_MS (10 * ONE_MS) #define GICD_BASE 0x1c81000 #define GICC_BASE 0x1c82000 diff --git a/arch/arm/cpu/armv7/sunxi/usbc.c b/arch/arm/cpu/armv7/sunxi/usbc.c index 14de9f9..524f25c 100644 --- a/arch/arm/cpu/armv7/sunxi/usbc.c +++ b/arch/arm/cpu/armv7/sunxi/usbc.c @@ -182,6 +182,13 @@ static void sunxi_usb_passby(struct sunxi_usbc_hcd *sunxi_usbc, int enable) return; } +void sunxi_usbc_enable_squelch_detect(int index, int enable) +{ + struct sunxi_usbc_hcd *sunxi_usbc = &sunxi_usbc_hcd[index]; + + usb_phy_write(sunxi_usbc, 0x3c, enable ? 0 : 2, 2); +} + int sunxi_usbc_request_resources(int index) { struct sunxi_usbc_hcd *sunxi_usbc = &sunxi_usbc_hcd[index]; diff --git a/arch/arm/cpu/tegra210-common/pinmux.c b/arch/arm/cpu/tegra210-common/pinmux.c deleted file mode 100644 index a29c76b..0000000 --- a/arch/arm/cpu/tegra210-common/pinmux.c +++ /dev/null @@ -1,195 +0,0 @@ -/* - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/pinmux.h> - -#define PIN(pin, f0, f1, f2, f3) \ - { \ - .funcs = { \ - PMUX_FUNC_##f0, \ - PMUX_FUNC_##f1, \ - PMUX_FUNC_##f2, \ - PMUX_FUNC_##f3, \ - }, \ - } - -#define PIN_RESERVED {} - -static const struct pmux_pingrp_desc tegra210_pingroups[] = { - /* pin, f0, f1, f2, f3 */ - /* Offset 0x3000 */ - PIN(SDMMC1_CLK_PM0, SDMMC1, RSVD1, RSVD2, RSVD3), - PIN(SDMMC1_CMD_PM1, SDMMC1, SPI3, RSVD2, RSVD3), - PIN(SDMMC1_DAT3_PM2, SDMMC1, SPI3, RSVD2, RSVD3), - PIN(SDMMC1_DAT2_PM3, SDMMC1, SPI3, RSVD2, RSVD3), - PIN(SDMMC1_DAT1_PM4, SDMMC1, SPI3, RSVD2, RSVD3), - PIN(SDMMC1_DAT0_PM5, SDMMC1, RSVD1, RSVD2, RSVD3), - PIN_RESERVED, - /* Offset 0x301c */ - PIN(SDMMC3_CLK_PP0, SDMMC3, RSVD1, RSVD2, RSVD3), - PIN(SDMMC3_CMD_PP1, SDMMC3, RSVD1, RSVD2, RSVD3), - PIN(SDMMC3_DAT0_PP5, SDMMC3, RSVD1, RSVD2, RSVD3), - PIN(SDMMC3_DAT1_PP4, SDMMC3, RSVD1, RSVD2, RSVD3), - PIN(SDMMC3_DAT2_PP3, SDMMC3, RSVD1, RSVD2, RSVD3), - PIN(SDMMC3_DAT3_PP2, SDMMC3, RSVD1, RSVD2, RSVD3), - PIN_RESERVED, - /* Offset 0x3038 */ - PIN(PEX_L0_RST_N_PA0, PE0, RSVD1, RSVD2, RSVD3), - PIN(PEX_L0_CLKREQ_N_PA1, PE0, RSVD1, RSVD2, RSVD3), - PIN(PEX_WAKE_N_PA2, PE, RSVD1, RSVD2, RSVD3), - PIN(PEX_L1_RST_N_PA3, PE1, RSVD1, RSVD2, RSVD3), - PIN(PEX_L1_CLKREQ_N_PA4, PE1, RSVD1, RSVD2, RSVD3), - PIN(SATA_LED_ACTIVE_PA5, SATA, RSVD1, RSVD2, RSVD3), - PIN(SPI1_MOSI_PC0, SPI1, RSVD1, RSVD2, RSVD3), - PIN(SPI1_MISO_PC1, SPI1, RSVD1, RSVD2, RSVD3), - PIN(SPI1_SCK_PC2, SPI1, RSVD1, RSVD2, RSVD3), - PIN(SPI1_CS0_PC3, SPI1, RSVD1, RSVD2, RSVD3), - PIN(SPI1_CS1_PC4, SPI1, RSVD1, RSVD2, RSVD3), - PIN(SPI2_MOSI_PB4, SPI2, DTV, RSVD2, RSVD3), - PIN(SPI2_MISO_PB5, SPI2, DTV, RSVD2, RSVD3), - PIN(SPI2_SCK_PB6, SPI2, DTV, RSVD2, RSVD3), - PIN(SPI2_CS0_PB7, SPI2, DTV, RSVD2, RSVD3), - PIN(SPI2_CS1_PDD0, SPI2, RSVD1, RSVD2, RSVD3), - PIN(SPI4_MOSI_PC7, SPI4, RSVD1, RSVD2, RSVD3), - PIN(SPI4_MISO_PD0, SPI4, RSVD1, RSVD2, RSVD3), - PIN(SPI4_SCK_PC5, SPI4, RSVD1, RSVD2, RSVD3), - PIN(SPI4_CS0_PC6, SPI4, RSVD1, RSVD2, RSVD3), - PIN(QSPI_SCK_PEE0, QSPI, RSVD1, RSVD2, RSVD3), - PIN(QSPI_CS_N_PEE1, QSPI, RSVD1, RSVD2, RSVD3), - PIN(QSPI_IO0_PEE2, QSPI, RSVD1, RSVD2, RSVD3), - PIN(QSPI_IO1_PEE3, QSPI, RSVD1, RSVD2, RSVD3), - PIN(QSPI_IO2_PEE4, QSPI, RSVD1, RSVD2, RSVD3), - PIN(QSPI_IO3_PEE5, QSPI, RSVD1, RSVD2, RSVD3), - PIN_RESERVED, - /* Offset 0x30a4 */ - PIN(DMIC1_CLK_PE0, DMIC1, I2S3, RSVD2, RSVD3), - PIN(DMIC1_DAT_PE1, DMIC1, I2S3, RSVD2, RSVD3), - PIN(DMIC2_CLK_PE2, DMIC2, I2S3, RSVD2, RSVD3), - PIN(DMIC2_DAT_PE3, DMIC2, I2S3, RSVD2, RSVD3), - PIN(DMIC3_CLK_PE4, DMIC3, I2S5A, RSVD2, RSVD3), - PIN(DMIC3_DAT_PE5, DMIC3, I2S5A, RSVD2, RSVD3), - PIN(GEN1_I2C_SCL_PJ1, I2C1, RSVD1, RSVD2, RSVD3), - PIN(GEN1_I2C_SDA_PJ0, I2C1, RSVD1, RSVD2, RSVD3), - PIN(GEN2_I2C_SCL_PJ2, I2C2, RSVD1, RSVD2, RSVD3), - PIN(GEN2_I2C_SDA_PJ3, I2C2, RSVD1, RSVD2, RSVD3), - PIN(GEN3_I2C_SCL_PF0, I2C3, RSVD1, RSVD2, RSVD3), - PIN(GEN3_I2C_SDA_PF1, I2C3, RSVD1, RSVD2, RSVD3), - PIN(CAM_I2C_SCL_PS2, I2C3, I2CVI, RSVD2, RSVD3), - PIN(CAM_I2C_SDA_PS3, I2C3, I2CVI, RSVD2, RSVD3), - PIN(PWR_I2C_SCL_PY3, I2CPMU, RSVD1, RSVD2, RSVD3), - PIN(PWR_I2C_SDA_PY4, I2CPMU, RSVD1, RSVD2, RSVD3), - PIN(UART1_TX_PU0, UARTA, RSVD1, RSVD2, RSVD3), - PIN(UART1_RX_PU1, UARTA, RSVD1, RSVD2, RSVD3), - PIN(UART1_RTS_PU2, UARTA, RSVD1, RSVD2, RSVD3), - PIN(UART1_CTS_PU3, UARTA, RSVD1, RSVD2, RSVD3), - PIN(UART2_TX_PG0, UARTB, I2S4A, SPDIF, UART), - PIN(UART2_RX_PG1, UARTB, I2S4A, SPDIF, UART), - PIN(UART2_RTS_PG2, UARTB, I2S4A, RSVD2, UART), - PIN(UART2_CTS_PG3, UARTB, I2S4A, RSVD2, UART), - PIN(UART3_TX_PD1, UARTC, SPI4, RSVD2, RSVD3), - PIN(UART3_RX_PD2, UARTC, SPI4, RSVD2, RSVD3), - PIN(UART3_RTS_PD3, UARTC, SPI4, RSVD2, RSVD3), - PIN(UART3_CTS_PD4, UARTC, SPI4, RSVD2, RSVD3), - PIN(UART4_TX_PI4, UARTD, UART, RSVD2, RSVD3), - PIN(UART4_RX_PI5, UARTD, UART, RSVD2, RSVD3), - PIN(UART4_RTS_PI6, UARTD, UART, RSVD2, RSVD3), - PIN(UART4_CTS_PI7, UARTD, UART, RSVD2, RSVD3), - PIN(DAP1_FS_PB0, I2S1, RSVD1, RSVD2, RSVD3), - PIN(DAP1_DIN_PB1, I2S1, RSVD1, RSVD2, RSVD3), - PIN(DAP1_DOUT_PB2, I2S1, RSVD1, RSVD2, RSVD3), - PIN(DAP1_SCLK_PB3, I2S1, RSVD1, RSVD2, RSVD3), - PIN(DAP2_FS_PAA0, I2S2, RSVD1, RSVD2, RSVD3), - PIN(DAP2_DIN_PAA2, I2S2, RSVD1, RSVD2, RSVD3), - PIN(DAP2_DOUT_PAA3, I2S2, RSVD1, RSVD2, RSVD3), - PIN(DAP2_SCLK_PAA1, I2S2, RSVD1, RSVD2, RSVD3), - PIN(DAP4_FS_PJ4, I2S4B, RSVD1, RSVD2, RSVD3), - PIN(DAP4_DIN_PJ5, I2S4B, RSVD1, RSVD2, RSVD3), - PIN(DAP4_DOUT_PJ6, I2S4B, RSVD1, RSVD2, RSVD3), - PIN(DAP4_SCLK_PJ7, I2S4B, RSVD1, RSVD2, RSVD3), - PIN(CAM1_MCLK_PS0, EXTPERIPH3, RSVD1, RSVD2, RSVD3), - PIN(CAM2_MCLK_PS1, EXTPERIPH3, RSVD1, RSVD2, RSVD3), - PIN(JTAG_RTCK, JTAG, RSVD1, RSVD2, RSVD3), - PIN(CLK_32K_IN, CLK, RSVD1, RSVD2, RSVD3), - PIN(CLK_32K_OUT_PY5, SOC, BLINK, RSVD2, RSVD3), - PIN(BATT_BCL, BCL, RSVD1, RSVD2, RSVD3), - PIN(CLK_REQ, SYS, RSVD1, RSVD2, RSVD3), - PIN(CPU_PWR_REQ, CPU, RSVD1, RSVD2, RSVD3), - PIN(PWR_INT_N, PMI, RSVD1, RSVD2, RSVD3), - PIN(SHUTDOWN, SHUTDOWN, RSVD1, RSVD2, RSVD3), - PIN(CORE_PWR_REQ, CORE, RSVD1, RSVD2, RSVD3), - PIN(AUD_MCLK_PBB0, AUD, RSVD1, RSVD2, RSVD3), - PIN(DVFS_PWM_PBB1, RSVD0, CLDVFS, SPI3, RSVD3), - PIN(DVFS_CLK_PBB2, RSVD0, CLDVFS, SPI3, RSVD3), - PIN(GPIO_X1_AUD_PBB3, RSVD0, RSVD1, SPI3, RSVD3), - PIN(GPIO_X3_AUD_PBB4, RSVD0, RSVD1, SPI3, RSVD3), - PIN(PCC7, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(HDMI_CEC_PCC0, CEC, RSVD1, RSVD2, RSVD3), - PIN(HDMI_INT_DP_HPD_PCC1, DP, RSVD1, RSVD2, RSVD3), - PIN(SPDIF_OUT_PCC2, SPDIF, RSVD1, RSVD2, RSVD3), - PIN(SPDIF_IN_PCC3, SPDIF, RSVD1, RSVD2, RSVD3), - PIN(USB_VBUS_EN0_PCC4, USB, RSVD1, RSVD2, RSVD3), - PIN(USB_VBUS_EN1_PCC5, USB, RSVD1, RSVD2, RSVD3), - PIN(DP_HPD0_PCC6, DP, RSVD1, RSVD2, RSVD3), - PIN(WIFI_EN_PH0, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(WIFI_RST_PH1, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(WIFI_WAKE_AP_PH2, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(AP_WAKE_BT_PH3, RSVD0, UARTB, SPDIF, RSVD3), - PIN(BT_RST_PH4, RSVD0, UARTB, SPDIF, RSVD3), - PIN(BT_WAKE_AP_PH5, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(AP_WAKE_NFC_PH7, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(NFC_EN_PI0, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(NFC_INT_PI1, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(GPS_EN_PI2, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(GPS_RST_PI3, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(CAM_RST_PS4, VGP1, RSVD1, RSVD2, RSVD3), - PIN(CAM_AF_EN_PS5, VIMCLK, VGP2, RSVD2, RSVD3), - PIN(CAM_FLASH_EN_PS6, VIMCLK, VGP3, RSVD2, RSVD3), - PIN(CAM1_PWDN_PS7, VGP4, RSVD1, RSVD2, RSVD3), - PIN(CAM2_PWDN_PT0, VGP5, RSVD1, RSVD2, RSVD3), - PIN(CAM1_STROBE_PT1, VGP6, RSVD1, RSVD2, RSVD3), - PIN(LCD_TE_PY2, DISPLAYA, RSVD1, RSVD2, RSVD3), - PIN(LCD_BL_PWM_PV0, DISPLAYA, PWM0, SOR0, RSVD3), - PIN(LCD_BL_EN_PV1, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(LCD_RST_PV2, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(LCD_GPIO1_PV3, DISPLAYB, RSVD1, RSVD2, RSVD3), - PIN(LCD_GPIO2_PV4, DISPLAYB, PWM1, RSVD2, SOR1), - PIN(AP_READY_PV5, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(TOUCH_RST_PV6, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(TOUCH_CLK_PV7, TOUCH, RSVD1, RSVD2, RSVD3), - PIN(MODEM_WAKE_AP_PX0, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(TOUCH_INT_PX1, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(MOTION_INT_PX2, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(ALS_PROX_INT_PX3, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(TEMP_ALERT_PX4, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(BUTTON_POWER_ON_PX5, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(BUTTON_VOL_UP_PX6, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(BUTTON_VOL_DOWN_PX7, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(BUTTON_SLIDE_SW_PY0, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(BUTTON_HOME_PY1, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(PA6, SATA, RSVD1, RSVD2, RSVD3), - PIN(PE6, RSVD0, I2S5A, PWM2, RSVD3), - PIN(PE7, RSVD0, I2S5A, PWM3, RSVD3), - PIN(PH6, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(PK0, IQC0, I2S5B, RSVD2, RSVD3), - PIN(PK1, IQC0, I2S5B, RSVD2, RSVD3), - PIN(PK2, IQC0, I2S5B, RSVD2, RSVD3), - PIN(PK3, IQC0, I2S5B, RSVD2, RSVD3), - PIN(PK4, IQC1, RSVD1, RSVD2, RSVD3), - PIN(PK5, IQC1, RSVD1, RSVD2, RSVD3), - PIN(PK6, IQC1, RSVD1, RSVD2, RSVD3), - PIN(PK7, IQC1, RSVD1, RSVD2, RSVD3), - PIN(PL0, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(PL1, SOC, RSVD1, RSVD2, RSVD3), - PIN(PZ0, VIMCLK2, RSVD1, RSVD2, RSVD3), - PIN(PZ1, VIMCLK2, SDMMC1, RSVD2, RSVD3), - PIN(PZ2, SDMMC3, CCLA, RSVD2, RSVD3), - PIN(PZ3, SDMMC3, RSVD1, RSVD2, RSVD3), - PIN(PZ4, SDMMC1, RSVD1, RSVD2, RSVD3), - PIN(PZ5, SOC, RSVD1, RSVD2, RSVD3), -}; -const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra210_pingroups; |