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| author | Peng Fan <Peng.Fan@freescale.com> | 2014-09-05 10:40:11 +0800 |
|---|---|---|
| committer | Peng Fan <Peng.Fan@freescale.com> | 2014-09-05 10:40:11 +0800 |
| commit | aa76a7e472e34bc59554f9932d611b1047d24590 (patch) | |
| tree | 3a07b7f43cbbecf0d443847751d707700618d53f /arch/arm/cpu | |
| parent | 0338ad3a375c4809abde523d9adfd689cc1f83cf (diff) | |
| download | u-boot-imx-aa76a7e472e34bc59554f9932d611b1047d24590.zip u-boot-imx-aa76a7e472e34bc59554f9932d611b1047d24590.tar.gz u-boot-imx-aa76a7e472e34bc59554f9932d611b1047d24590.tar.bz2 | |
ENGR00329484-2 ARM:MX6: Clear Align bit in SCTLR
This problem is found when debugging QuadSPI. When "A" bit is enabled,
unaligned access will cause data abort exception. Actually, we do not
want this exception. So clear the align bit for MX6 SOCs.
Tested this code with android team colleague and did not find problem.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Diffstat (limited to 'arch/arm/cpu')
| -rw-r--r-- | arch/arm/cpu/armv7/mx6/soc.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 4787fb2..2fae6f4 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -477,6 +477,9 @@ static void imx_set_pcie_phy_power_down(void) int arch_cpu_init(void) { + /* Clear the Align bit in SCTLR */ + set_cr(get_cr() & ~CR_A); + #if !defined(CONFIG_MX6SX) && !defined(CONFIG_MX6SL) /* * imx6sl doesn't have pcie at all. |