am33xx: Correct and clean up ddr_regs struct

The ddr_regs struct was incorrectly offset after the dt0wiratio0 entry.
Correct this by documenting a missing register that will be used at some
point in the future (when write leveling is supported).  Further, the
cmdNcs{force,delay} fields are undocumented and we have been setting
them to zero, remove.  Next, setting of the
'DATAn_REG_PHY_USE_RANK0_DELAYS field belongs with the rest of the
ddr_data entries, so program it there.  Finally, comment on how we are
configuring the DATA1 registers that correspond to the DATA0 (dt0)
registers defined in the struct.

Signed-off-by: Tom Rini <trini@ti.com>

2 files changed, 2 insertions, 15 deletions

diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c
index 59ca51f..bceed81 100644
--- a/arch/arm/cpu/armv7/am33xx/ddr.c
+++ b/arch/arm/cpu/armv7/am33xx/ddr.c
@@ -77,20 +77,14 @@ void config_ddr_phy(const struct emif_regs *regs)
 void config_cmd_ctrl(const struct cmd_control *cmd)
 {
 	writel(cmd->cmd0csratio, &ddr_reg[0]->cm0csratio);
-	writel(cmd->cmd0csforce, &ddr_reg[0]->cm0csforce);
-	writel(cmd->cmd0csdelay, &ddr_reg[0]->cm0csdelay);
 	writel(cmd->cmd0dldiff, &ddr_reg[0]->cm0dldiff);
 	writel(cmd->cmd0iclkout, &ddr_reg[0]->cm0iclkout);
 
 	writel(cmd->cmd1csratio, &ddr_reg[0]->cm1csratio);
-	writel(cmd->cmd1csforce, &ddr_reg[0]->cm1csforce);
-	writel(cmd->cmd1csdelay, &ddr_reg[0]->cm1csdelay);
 	writel(cmd->cmd1dldiff, &ddr_reg[0]->cm1dldiff);
 	writel(cmd->cmd1iclkout, &ddr_reg[0]->cm1iclkout);
 
 	writel(cmd->cmd2csratio, &ddr_reg[0]->cm2csratio);
-	writel(cmd->cmd2csforce, &ddr_reg[0]->cm2csforce);
-	writel(cmd->cmd2csdelay, &ddr_reg[0]->cm2csdelay);
 	writel(cmd->cmd2dldiff, &ddr_reg[0]->cm2dldiff);
 	writel(cmd->cmd2iclkout, &ddr_reg[0]->cm2iclkout);
 }
@@ -106,6 +100,7 @@ void config_ddr_data(int macrono, const struct ddr_data *data)
 	writel(data->datagiratio0, &ddr_reg[macrono]->dt0giratio0);
 	writel(data->datafwsratio0, &ddr_reg[macrono]->dt0fwsratio0);
 	writel(data->datawrsratio0, &ddr_reg[macrono]->dt0wrsratio0);
+	writel(data->datauserank0delay, &ddr_reg[macrono]->dt0rdelays0);
 	writel(data->datadldiff0, &ddr_reg[macrono]->dt0dldiff0);
 }
 
diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c
index ace3d26..3bb91d3 100644
--- a/arch/arm/cpu/armv7/am33xx/emif4.c
+++ b/arch/arm/cpu/armv7/am33xx/emif4.c
@@ -61,25 +61,20 @@ static const struct ddr_data ddr2_data = {
 				|(DDR2_PHY_FIFO_WE<<10)|(DDR2_PHY_FIFO_WE<<0)),
 	.datawrsratio0 = ((DDR2_PHY_WR_DATA<<30)|(DDR2_PHY_WR_DATA<<20)
 				|(DDR2_PHY_WR_DATA<<10)|(DDR2_PHY_WR_DATA<<0)),
+	.datauserank0delay = DDR2_PHY_RANK0_DELAY,
 	.datadldiff0 = PHY_DLL_LOCK_DIFF,
 };
 
 static const struct cmd_control ddr2_cmd_ctrl_data = {
 	.cmd0csratio = DDR2_RATIO,
-	.cmd0csforce = CMD_FORCE,
-	.cmd0csdelay = CMD_DELAY,
 	.cmd0dldiff = DDR2_DLL_LOCK_DIFF,
 	.cmd0iclkout = DDR2_INVERT_CLKOUT,
 
 	.cmd1csratio = DDR2_RATIO,
-	.cmd1csforce = CMD_FORCE,
-	.cmd1csdelay = CMD_DELAY,
 	.cmd1dldiff = DDR2_DLL_LOCK_DIFF,
 	.cmd1iclkout = DDR2_INVERT_CLKOUT,
 
 	.cmd2csratio = DDR2_RATIO,
-	.cmd2csforce = CMD_FORCE,
-	.cmd2csdelay = CMD_DELAY,
 	.cmd2dldiff = DDR2_DLL_LOCK_DIFF,
 	.cmd2iclkout = DDR2_INVERT_CLKOUT,
 };
@@ -121,9 +116,6 @@ void config_ddr(short ddr_type)
 		config_ddr_data(0, &ddr2_data);
 		config_ddr_data(1, &ddr2_data);
 
-		writel(DDR2_PHY_RANK0_DELAY, &ddrregs->dt0rdelays0);
-		writel(DDR2_PHY_RANK0_DELAY, &ddrregs->dt1rdelays0);
-
 		config_io_ctrl(DDR2_IOCTRL_VALUE);
 
 		/* Set CKE to be controlled by EMIF/DDR PHY */