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author | Hou Zhiqiang <Zhiqiang.Hou@nxp.com> | 2016-06-28 20:18:12 +0800 |
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committer | York Sun <york.sun@nxp.com> | 2016-07-19 11:32:43 -0700 |
commit | 85cdf38e69bbf3b2bb67c8218c8e4cbf28f8759b (patch) | |
tree | ee799656cdd9adce32cb78d4987ec909a6686a50 /arch/arm/cpu | |
parent | 5ad5823d0c71a45f886d0016a74d62a5216abe10 (diff) | |
download | u-boot-imx-85cdf38e69bbf3b2bb67c8218c8e4cbf28f8759b.zip u-boot-imx-85cdf38e69bbf3b2bb67c8218c8e4cbf28f8759b.tar.gz u-boot-imx-85cdf38e69bbf3b2bb67c8218c8e4cbf28f8759b.tar.bz2 |
armv8: fsl-layerscape: add i/d-cache enable function to enable_caches
This function assume that the d-cache and MMU has been enabled earlier,
so it just created MMU table in main memory. But the assumption is not
always correct, for example, the early setup is done in EL3, while
enable_caches() is called when the PE has turned into another EL.
Define the function mmu_setup() for fsl-layerscape to cover the weak
one.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/arm/cpu')
-rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 14 |
1 files changed, 10 insertions, 4 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index b6ebedc..bcedf2c 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -164,15 +164,21 @@ int arch_cpu_init(void) return 0; } +void mmu_setup(void) +{ + final_mmu_setup(); +} + /* - * This function is called from lib/board.c. - * It recreates MMU table in main memory. MMU and d-cache are enabled earlier. - * There is no need to disable d-cache for this operation. + * This function is called from common/board_r.c. + * It recreates MMU table in main memory. */ void enable_caches(void) { - final_mmu_setup(); + mmu_setup(); __asm_invalidate_tlb_all(); + icache_enable(); + dcache_enable(); } #endif |