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| author | Robert P. J. Day <rpjday@crashcourse.ca> | 2016-05-04 04:47:31 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2016-05-05 21:39:26 -0400 |
| commit | 1cc0a9f49657734c54939f03fc1e3ca0ec9d7eef (patch) | |
| tree | d33c7d4d02e251e1f02aad52c7c60157259c864e /arch/arm/cpu | |
| parent | b955e42bad81a2ddad2f82c1843771de9bdfe6d4 (diff) | |
| download | u-boot-imx-1cc0a9f49657734c54939f03fc1e3ca0ec9d7eef.zip u-boot-imx-1cc0a9f49657734c54939f03fc1e3ca0ec9d7eef.tar.gz u-boot-imx-1cc0a9f49657734c54939f03fc1e3ca0ec9d7eef.tar.bz2 | |
Fix various typos, scattered over the code.
Spelling corrections for (among other things):
* environment
* override
* variable
* ftd (should be "fdt", for flattened device tree)
* embedded
* FTDI
* emulation
* controller
Diffstat (limited to 'arch/arm/cpu')
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c index d580a43..a9b12a4 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c @@ -180,7 +180,7 @@ ulong get_ddr_freq(ulong ctrl_num) /* * DDR controller 0 & 1 are on memory complex 0 - * DDR controler 2 is on memory complext 1 + * DDR controller 2 is on memory complext 1 */ #ifdef CONFIG_SYS_FSL_HAS_DP_DDR if (ctrl_num >= 2) |