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| author | Shaohui Xie <Shaohui.Xie@nxp.com> | 2016-09-07 17:56:12 +0800 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2016-09-14 14:10:52 -0700 |
| commit | 1b2b406636b5643466552fdb4821eff1a76d8acb (patch) | |
| tree | d19b7db0e0f42ab0f00ffcacc4842a36f453ae6a /arch/arm/cpu | |
| parent | 5f5e8d92d56fb6d6bd792b067fe8931259d1b99a (diff) | |
| download | u-boot-imx-1b2b406636b5643466552fdb4821eff1a76d8acb.zip u-boot-imx-1b2b406636b5643466552fdb4821eff1a76d8acb.tar.gz u-boot-imx-1b2b406636b5643466552fdb4821eff1a76d8acb.tar.bz2 | |
armv8: ls1046a: disable SATA ECC in DCSR
This is a workaround to fix SATA CRC error. Once the root cause
is found the ECC disabling will be removed.
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/arm/cpu')
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/soc.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 43c4aa5..5ca721d 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -228,6 +228,10 @@ int sata_init(void) { struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA; +#ifdef CONFIG_LS1046A + /* Disable SATA ECC */ + out_le32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + 0x520, 0x80000000); +#endif out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY_2_CFG); out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY_3_CFG); |