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| author | Simon Glass <sjg@chromium.org> | 2011-09-21 12:40:02 +0000 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2011-10-27 21:56:29 +0200 |
| commit | 03c609f69b12dca47b9422595fdde29be1fb35c9 (patch) | |
| tree | aa4e9f2bb9ac562ace58b5891d7001704ef8d812 /arch/arm/cpu | |
| parent | c30a15e590c7e5bfd27e4704c81648071f11d51f (diff) | |
| download | u-boot-imx-03c609f69b12dca47b9422595fdde29be1fb35c9.zip u-boot-imx-03c609f69b12dca47b9422595fdde29be1fb35c9.tar.gz u-boot-imx-03c609f69b12dca47b9422595fdde29be1fb35c9.tar.bz2 | |
tegra2: Rename CLOCK_PLL_ID to CLOCK_ID
Rename CLOCK_PLL_ID to CLOCK_ID which takes account of the fact that the
code now deals with both PLL clocks and source clocks.
This also tidied up the assert() to match the one sent upstream, and fixes
an error in the PWM id.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'arch/arm/cpu')
| -rw-r--r-- | arch/arm/cpu/armv7/tegra2/ap20.c | 2 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/tegra2/clock.c | 6 |
2 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/cpu/armv7/tegra2/ap20.c b/arch/arm/cpu/armv7/tegra2/ap20.c index dc5f984..64d4c69 100644 --- a/arch/arm/cpu/armv7/tegra2/ap20.c +++ b/arch/arm/cpu/armv7/tegra2/ap20.c @@ -36,7 +36,7 @@ u32 s_first_boot = 1; void init_pllx(void) { struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; - struct clk_pll *pll = &clkrst->crc_pll[CLOCK_PLL_ID_XCPU]; + struct clk_pll *pll = &clkrst->crc_pll[CLOCK_ID_XCPU]; u32 reg; /* If PLLX is already enabled, just return */ diff --git a/arch/arm/cpu/armv7/tegra2/clock.c b/arch/arm/cpu/armv7/tegra2/clock.c index 0aaed7d..5aa6482 100644 --- a/arch/arm/cpu/armv7/tegra2/clock.c +++ b/arch/arm/cpu/armv7/tegra2/clock.c @@ -42,7 +42,7 @@ enum clock_osc_freq clock_get_osc_freq(void) return (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT; } -unsigned long clock_start_pll(enum clock_pll_id clkid, u32 divm, u32 divn, +unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn, u32 divp, u32 cpcon, u32 lfcon) { struct clk_rst_ctlr *clkrst = @@ -50,7 +50,7 @@ unsigned long clock_start_pll(enum clock_pll_id clkid, u32 divm, u32 divn, u32 data; struct clk_pll *pll; - assert(clock_pll_id_isvalid(clkid)); + assert(clock_id_isvalid(clkid)); pll = &clkrst->crc_pll[clkid]; /* @@ -66,7 +66,7 @@ unsigned long clock_start_pll(enum clock_pll_id clkid, u32 divm, u32 divn, data = (divm << PLL_DIVM_SHIFT) | (divn << PLL_DIVN_SHIFT) | (0 << PLL_BYPASS_SHIFT) | (1 << PLL_ENABLE_SHIFT); - if (clkid == CLOCK_PLL_ID_USB) + if (clkid == CLOCK_ID_USB) data |= divp << PLLU_VCO_FREQ_SHIFT; else data |= divp << PLL_DIVP_SHIFT; |