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| author | Tom Rini <trini@ti.com> | 2014-12-16 09:41:00 -0500 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2014-12-16 09:41:00 -0500 |
| commit | 3bfbf32b6fe5e2d4605bc7ee99d1844b572662c2 (patch) | |
| tree | 6d13141b70a8961bc6ff67cec8a9c6e167d96bfb /arch/arm/cpu | |
| parent | b9206e61f3d87535ac4f4b0b858e674fd1edfeaf (diff) | |
| parent | 065496d1b5304a6a67b366b613c3504aab2e2dbd (diff) | |
| download | u-boot-imx-3bfbf32b6fe5e2d4605bc7ee99d1844b572662c2.zip u-boot-imx-3bfbf32b6fe5e2d4605bc7ee99d1844b572662c2.tar.gz u-boot-imx-3bfbf32b6fe5e2d4605bc7ee99d1844b572662c2.tar.bz2 | |
Merge branch 'master' of git://git.denx.de/u-boot-socfpga
Diffstat (limited to 'arch/arm/cpu')
| -rw-r--r-- | arch/arm/cpu/armv7/socfpga/freeze_controller.c | 6 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/socfpga/reset_manager.c | 4 |
2 files changed, 4 insertions, 6 deletions
diff --git a/arch/arm/cpu/armv7/socfpga/freeze_controller.c b/arch/arm/cpu/armv7/socfpga/freeze_controller.c index b8c9bce..0be643c 100644 --- a/arch/arm/cpu/armv7/socfpga/freeze_controller.c +++ b/arch/arm/cpu/armv7/socfpga/freeze_controller.c @@ -38,8 +38,7 @@ void sys_mgr_frzctrl_freeze_req(void) /* Freeze channel 0 to 2 */ for (channel_id = 0; channel_id <= 2; channel_id++) { ioctrl_reg_offset = (u32)( - &freeze_controller_base->vioctrl + - (channel_id << SYSMGR_FRZCTRL_VIOCTRL_SHIFT)); + &freeze_controller_base->vioctrl + channel_id); /* * Assert active low enrnsl, plniotri @@ -120,8 +119,7 @@ void sys_mgr_frzctrl_thaw_req(void) /* Thaw channel 0 to 2 */ for (channel_id = 0; channel_id <= 2; channel_id++) { ioctrl_reg_offset - = (u32)(&freeze_controller_base->vioctrl - + (channel_id << SYSMGR_FRZCTRL_VIOCTRL_SHIFT)); + = (u32)(&freeze_controller_base->vioctrl + channel_id); /* * Assert active low bhniotri signal and diff --git a/arch/arm/cpu/armv7/socfpga/reset_manager.c b/arch/arm/cpu/armv7/socfpga/reset_manager.c index af9db85..25921e7 100644 --- a/arch/arm/cpu/armv7/socfpga/reset_manager.c +++ b/arch/arm/cpu/armv7/socfpga/reset_manager.c @@ -110,6 +110,6 @@ void socfpga_spim_enable(void) { const void *reset = &reset_manager_base->per_mod_reset; - clrbits_le32(reset, 1 << RSTMGR_PERMODRST_SPIM0_LSB); - clrbits_le32(reset, 1 << RSTMGR_PERMODRST_SPIM1_LSB); + clrbits_le32(reset, (1 << RSTMGR_PERMODRST_SPIM0_LSB) | + (1 << RSTMGR_PERMODRST_SPIM1_LSB)); } |