From c877eaa8a04858c23ce7ebb82c59f7cf838545ef Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Sun, 16 Nov 2014 12:46:59 +0100 Subject: arm: socfpga: Use only one clrbits_le32 call to deassert SPI reset bits As suggested by Pavel, lets combine the two calls into one. Signed-off-by: Stefan Roese Cc: Chin Liang See Cc: Dinh Nguyen Cc: Vince Bridgers Cc: Marek Vasut Acked-by: Pavel Machek --- arch/arm/cpu/armv7/socfpga/reset_manager.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/cpu') diff --git a/arch/arm/cpu/armv7/socfpga/reset_manager.c b/arch/arm/cpu/armv7/socfpga/reset_manager.c index af9db85..25921e7 100644 --- a/arch/arm/cpu/armv7/socfpga/reset_manager.c +++ b/arch/arm/cpu/armv7/socfpga/reset_manager.c @@ -110,6 +110,6 @@ void socfpga_spim_enable(void) { const void *reset = &reset_manager_base->per_mod_reset; - clrbits_le32(reset, 1 << RSTMGR_PERMODRST_SPIM0_LSB); - clrbits_le32(reset, 1 << RSTMGR_PERMODRST_SPIM1_LSB); + clrbits_le32(reset, (1 << RSTMGR_PERMODRST_SPIM0_LSB) | + (1 << RSTMGR_PERMODRST_SPIM1_LSB)); } -- cgit v1.1 From b9b5cf0ea3c5c141f31cc0c4c8edebbfd9ff5866 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Wed, 26 Nov 2014 12:14:33 -0600 Subject: socfpga: correctly increment freeze_controller_base address Correctly increment the base address of the freeze controller. And since SYSMGR_FRZCTRL_VIOCTRL_SHIFT is not needed, remove it from the include file. Signed-off-by: Dinh Nguyen Cc: Vince Bridgers Cc: Chin Liang See Cc: Marek Vasut Acked-by: Pavel Machek Cc: Wolfgang Denk --- arch/arm/cpu/armv7/socfpga/freeze_controller.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'arch/arm/cpu') diff --git a/arch/arm/cpu/armv7/socfpga/freeze_controller.c b/arch/arm/cpu/armv7/socfpga/freeze_controller.c index b8c9bce..0be643c 100644 --- a/arch/arm/cpu/armv7/socfpga/freeze_controller.c +++ b/arch/arm/cpu/armv7/socfpga/freeze_controller.c @@ -38,8 +38,7 @@ void sys_mgr_frzctrl_freeze_req(void) /* Freeze channel 0 to 2 */ for (channel_id = 0; channel_id <= 2; channel_id++) { ioctrl_reg_offset = (u32)( - &freeze_controller_base->vioctrl + - (channel_id << SYSMGR_FRZCTRL_VIOCTRL_SHIFT)); + &freeze_controller_base->vioctrl + channel_id); /* * Assert active low enrnsl, plniotri @@ -120,8 +119,7 @@ void sys_mgr_frzctrl_thaw_req(void) /* Thaw channel 0 to 2 */ for (channel_id = 0; channel_id <= 2; channel_id++) { ioctrl_reg_offset - = (u32)(&freeze_controller_base->vioctrl - + (channel_id << SYSMGR_FRZCTRL_VIOCTRL_SHIFT)); + = (u32)(&freeze_controller_base->vioctrl + channel_id); /* * Assert active low bhniotri signal and -- cgit v1.1