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authorTom Warren <twarren.nvidia@gmail.com>2014-01-24 10:16:22 -0700
committerTom Warren <twarren@nvidia.com>2014-02-03 09:46:45 -0700
commitc82014daf5ed8030d2ec5903bd51b5ab817fb000 (patch)
tree6f3ef330baf44f4cbc6bfa304b9d557e0c074dac /arch/arm/cpu/tegra-common
parent04b8e8e7452a4cd00003e33a5a736bd077ff3471 (diff)
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ARM: tegra: implement MASK_BITS_31_29
Some clock sources have 3-bit muxes in bits 31:29. Implement core support for this mux field. Signed-off-by: Tom Warren <twarren@nvidia.com> [swarren, extracted from a larger patch by Tom] Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'arch/arm/cpu/tegra-common')
-rw-r--r--arch/arm/cpu/tegra-common/clock.c22
1 files changed, 18 insertions, 4 deletions
diff --git a/arch/arm/cpu/tegra-common/clock.c b/arch/arm/cpu/tegra-common/clock.c
index 96b705f..33bb190 100644
--- a/arch/arm/cpu/tegra-common/clock.c
+++ b/arch/arm/cpu/tegra-common/clock.c
@@ -304,13 +304,27 @@ static int adjust_periph_pll(enum periph_id periph_id, int source,
/* work out the source clock and set it */
if (source < 0)
return -1;
- if (mux_bits == MASK_BITS_31_28) {
- clrsetbits_le32(reg, OUT_CLK_SOURCE_31_28_MASK,
- source << OUT_CLK_SOURCE_31_28_SHIFT);
- } else {
+
+ switch (mux_bits) {
+ case MASK_BITS_31_30:
clrsetbits_le32(reg, OUT_CLK_SOURCE_31_30_MASK,
source << OUT_CLK_SOURCE_31_30_SHIFT);
+ break;
+
+ case MASK_BITS_31_29:
+ clrsetbits_le32(reg, OUT_CLK_SOURCE_31_29_MASK,
+ source << OUT_CLK_SOURCE_31_29_SHIFT);
+ break;
+
+ case MASK_BITS_31_28:
+ clrsetbits_le32(reg, OUT_CLK_SOURCE_31_28_MASK,
+ source << OUT_CLK_SOURCE_31_28_SHIFT);
+ break;
+
+ default:
+ return -1;
}
+
udelay(2);
return 0;
}