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| author | Bryan Wu <pengw@nvidia.com> | 2014-06-24 11:45:29 +0900 |
|---|---|---|
| committer | Tom Warren <twarren@nvidia.com> | 2014-08-18 16:57:02 -0700 |
| commit | df3443dfa449ad02bef8ddf6e2c90a6fd9394fc9 (patch) | |
| tree | 208df055da17bf359f611abf18def134fb2c9a7b /arch/arm/cpu/tegra-common/ap.c | |
| parent | 1899fac925eda817e12234aef3d01d354788662e (diff) | |
| download | u-boot-imx-df3443dfa449ad02bef8ddf6e2c90a6fd9394fc9.zip u-boot-imx-df3443dfa449ad02bef8ddf6e2c90a6fd9394fc9.tar.gz u-boot-imx-df3443dfa449ad02bef8ddf6e2c90a6fd9394fc9.tar.bz2 | |
ARM: tegra: Disable VPR
On Tegra114 and Tegra124 platforms, certain display-related registers cannot
be accessed unless the VPR registers are programmed. For bootloader, we
probably don't care about VPR, so we disable it (which counts as programming
it, and allows those display-related registers to be accessed).
This patch is based on the commit 5f499646c83ba08079f3fdff6591f638a0ce4c0c
in Chromium OS U-Boot project.
Signed-off-by: Andrew Chew <achew@nvidia.com>
Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Signed-off-by: Bryan Wu <pengw@nvidia.com>
[acourbot: ensure write went through, vpr.c style changes]
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Cc: Tom Warren <TWarren@nvidia.com>
Cc: Stephen Warren <swarren@nvidia.com>
Cc: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'arch/arm/cpu/tegra-common/ap.c')
| -rw-r--r-- | arch/arm/cpu/tegra-common/ap.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/cpu/tegra-common/ap.c b/arch/arm/cpu/tegra-common/ap.c index 91d70da..a17dfd1 100644 --- a/arch/arm/cpu/tegra-common/ap.c +++ b/arch/arm/cpu/tegra-common/ap.c @@ -163,4 +163,7 @@ void s_init(void) /* init the cache */ config_cache(); + + /* init vpr */ + config_vpr(); } |