summaryrefslogtreecommitdiff
path: root/arch/arm/cpu/armv8
diff options
context:
space:
mode:
authorHou Zhiqiang <B48286@freescale.com>2015-10-26 19:47:57 +0800
committerYork Sun <yorksun@freescale.com>2015-10-29 10:34:02 -0700
commit831c068fcfe7d32e48a8b9052a137701b41c7d86 (patch)
treeca3620f5de92671c6d39acbce00b1af38e84e381 /arch/arm/cpu/armv8
parentc7ca8b07fcdd9af739fa3b1bfabe05d0da36c556 (diff)
downloadu-boot-imx-831c068fcfe7d32e48a8b9052a137701b41c7d86.zip
u-boot-imx-831c068fcfe7d32e48a8b9052a137701b41c7d86.tar.gz
u-boot-imx-831c068fcfe7d32e48a8b9052a137701b41c7d86.tar.bz2
armv8/ls1043a: Enable secondary cores
After the secondary cores enter U-Boot, use CONFIG_ARMV8_MULTIENTRY to make secondary cores excute in spin loop. Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch/arm/cpu/armv8')
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/mp.c14
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/mp.c b/arch/arm/cpu/armv8/fsl-layerscape/mp.c
index 1b13d32..0d600db 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/mp.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/mp.c
@@ -25,7 +25,11 @@ phys_addr_t determine_mp_bootpg(void)
int fsl_layerscape_wake_seconday_cores(void)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+#ifdef CONFIG_FSL_LSCH3
struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR);
+#elif defined(CONFIG_FSL_LSCH2)
+ struct ccsr_scfg __iomem *scfg = (void *)(CONFIG_SYS_FSL_SCFG_ADDR);
+#endif
u32 cores, cpu_up_mask = 1;
int i, timeout = 10;
u64 *table = get_spin_tbl_addr();
@@ -48,13 +52,23 @@ int fsl_layerscape_wake_seconday_cores(void)
printf("Waking secondary cores to start from %lx\n", gd->relocaddr);
+#ifdef CONFIG_FSL_LSCH3
gur_out32(&gur->bootlocptrh, (u32)(gd->relocaddr >> 32));
gur_out32(&gur->bootlocptrl, (u32)gd->relocaddr);
gur_out32(&gur->scratchrw[6], 1);
asm volatile("dsb st" : : : "memory");
rst->brrl = cores;
asm volatile("dsb st" : : : "memory");
+#elif defined(CONFIG_FSL_LSCH2)
+ scfg_out32(&scfg->scratchrw[0], (u32)(gd->relocaddr >> 32));
+ scfg_out32(&scfg->scratchrw[1], (u32)gd->relocaddr);
+ asm volatile("dsb st" : : : "memory");
+ gur_out32(&gur->brrl, cores);
+ asm volatile("dsb st" : : : "memory");
+ /* Bootup online cores */
+ scfg_out32(&scfg->corebcr, cores);
+#endif
/* This is needed as a precautionary measure.
* If some code before this has accidentally released the secondary
* cores then the pre-bootloader code will trap them in a "wfe" unless