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| author | Michal Simek <michal.simek@xilinx.com> | 2016-08-16 15:40:05 +0200 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2016-09-22 07:33:21 +0200 |
| commit | 5242772c5113850c0c35d6271fd281dfc669c707 (patch) | |
| tree | 2e934c85615d800d19965d1bb311e6ee0606001e /arch/arm/cpu/armv8/zynqmp | |
| parent | 48255f52764b64f35a268e4e87f2c3a621741836 (diff) | |
| download | u-boot-imx-5242772c5113850c0c35d6271fd281dfc669c707.zip u-boot-imx-5242772c5113850c0c35d6271fd281dfc669c707.tar.gz u-boot-imx-5242772c5113850c0c35d6271fd281dfc669c707.tar.bz2 | |
ARM64: zynqmp: Fix USB ulpi phy sequence
It should be enough to call low(5us)->high pulse for all cases
to provide proper reset. There is no need to call high->low->high.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'arch/arm/cpu/armv8/zynqmp')
| -rw-r--r-- | arch/arm/cpu/armv8/zynqmp/spl.c | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/arch/arm/cpu/armv8/zynqmp/spl.c b/arch/arm/cpu/armv8/zynqmp/spl.c index 552f577..04e1905 100644 --- a/arch/arm/cpu/armv8/zynqmp/spl.c +++ b/arch/arm/cpu/armv8/zynqmp/spl.c @@ -37,10 +37,6 @@ void board_init_f(ulong dummy) static void ps_mode_reset(ulong mode) { - writel(mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT | - mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT, - &crlapb_base->boot_pin_ctrl); - udelay(1); writel(mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT, &crlapb_base->boot_pin_ctrl); udelay(5); |