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author | Tom Rini <trini@konsulko.com> | 2017-01-19 12:22:23 -0500 |
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committer | Tom Rini <trini@konsulko.com> | 2017-01-19 12:22:23 -0500 |
commit | 0675f992dbf4a785a05a1baf149c2bce6aa5fe90 (patch) | |
tree | b8868ec70ff6b2b20f8f0fb87df9438906020a08 /arch/arm/cpu/armv8/sec_firmware_asm.S | |
parent | 755b06d1c0f3b16318c7580bec066efbb9ec6ccf (diff) | |
parent | 5e4a6db8f428cb1f8ced74bc77241144ac0c5b1a (diff) | |
download | u-boot-imx-0675f992dbf4a785a05a1baf149c2bce6aa5fe90.zip u-boot-imx-0675f992dbf4a785a05a1baf149c2bce6aa5fe90.tar.gz u-boot-imx-0675f992dbf4a785a05a1baf149c2bce6aa5fe90.tar.bz2 |
Merge git://git.denx.de/u-boot-fsl-qoriq
Diffstat (limited to 'arch/arm/cpu/armv8/sec_firmware_asm.S')
-rw-r--r-- | arch/arm/cpu/armv8/sec_firmware_asm.S | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/arm/cpu/armv8/sec_firmware_asm.S b/arch/arm/cpu/armv8/sec_firmware_asm.S index 903195d..30563eb 100644 --- a/arch/arm/cpu/armv8/sec_firmware_asm.S +++ b/arch/arm/cpu/armv8/sec_firmware_asm.S @@ -23,12 +23,12 @@ WEAK(_sec_firmware_entry) /* Set exception return address hold pointer */ adr x4, 1f mov x3, x4 -#ifdef SEC_FIRMWARE_ERET_ADDR_REVERT +#ifdef CONFIG_ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT rev w3, w3 #endif str w3, [x1] lsr x3, x4, #32 -#ifdef SEC_FIRMWARE_ERET_ADDR_REVERT +#ifdef CONFIG_ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT rev w3, w3 #endif str w3, [x2] @@ -41,7 +41,7 @@ WEAK(_sec_firmware_entry) ret ENDPROC(_sec_firmware_entry) -#ifdef CONFIG_FSL_PPA_ARMV8_PSCI +#ifdef CONFIG_SEC_FIRMWARE_ARMV8_PSCI ENTRY(_sec_firmware_support_psci_version) mov x0, 0x84000000 mov x1, 0x0 @@ -57,7 +57,8 @@ ENDPROC(_sec_firmware_support_psci_version) * x0: argument, zero * x1: machine nr * x2: fdt address - * x3: kernel entry point + * x3: input argument + * x4: kernel entry point * @param outputs for secure firmware: * x0: function id * x1: kernel entry point @@ -65,10 +66,9 @@ ENDPROC(_sec_firmware_support_psci_version) * x3: fdt address */ ENTRY(armv8_el2_to_aarch32) - mov x0, x3 mov x3, x2 mov x2, x1 - mov x1, x0 + mov x1, x4 ldr x0, =0xc000ff04 smc #0 ret |