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| author | York Sun <yorksun@freescale.com> | 2014-09-08 12:20:00 -0700 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2014-09-25 08:36:19 -0700 |
| commit | 40f8dec54d7803975aed1c88327002c95ea99908 (patch) | |
| tree | 83f7778c9179e518631ce308f3504a1e6e634c57 /arch/arm/cpu/armv8/fsl-lsch3/cpu.h | |
| parent | f43b4356a794be647011132f4f2dc970a29a9dd5 (diff) | |
| download | u-boot-imx-40f8dec54d7803975aed1c88327002c95ea99908.zip u-boot-imx-40f8dec54d7803975aed1c88327002c95ea99908.tar.gz u-boot-imx-40f8dec54d7803975aed1c88327002c95ea99908.tar.bz2 | |
armv8/fsl-lsch3: Release secondary cores from boot hold off with Boot Page
Secondary cores need to be released from holdoff by boot release
registers. With GPP bootrom, they can boot from main memory
directly. Individual spin table is used for each core. Spin table
and the boot page is reserved in device tree so OS won't overwrite.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
Diffstat (limited to 'arch/arm/cpu/armv8/fsl-lsch3/cpu.h')
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-lsch3/cpu.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.h b/arch/arm/cpu/armv8/fsl-lsch3/cpu.h index 28544d7..2e3312b 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.h +++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.h @@ -5,3 +5,4 @@ */ int fsl_qoriq_core_to_cluster(unsigned int core); +u32 cpu_mask(void); |