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| author | Yunhui Cui <yunhui.cui@nxp.com> | 2016-06-08 10:31:42 +0800 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2016-06-10 13:43:12 -0700 |
| commit | a758177f9b9a567df2e8e6e57ac905ada24d8d9c (patch) | |
| tree | b618ee8928ad9a9ff004a174d120f3066e3006e7 /arch/arm/cpu/armv8/fsl-layerscape | |
| parent | 6b3943f1b04be60f147ee540fbd72c4c7ea89f80 (diff) | |
| download | u-boot-imx-a758177f9b9a567df2e8e6e57ac905ada24d8d9c.zip u-boot-imx-a758177f9b9a567df2e8e6e57ac905ada24d8d9c.tar.gz u-boot-imx-a758177f9b9a567df2e8e6e57ac905ada24d8d9c.tar.bz2 | |
armv8/ls2080a: configure PMU's PCTBENR to enable WDT
The SP805-WDT module on LS2080A requires configuration of PMU's
PCTBENR register to enable watchdog counter decrement and reset
signal generation. The watchdog clock needs to be enabled first.
Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/arm/cpu/armv8/fsl-layerscape')
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 9a5a6b5..297687d 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -636,6 +636,9 @@ int timer_init(void) #ifdef CONFIG_FSL_LSCH3 u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR; #endif +#ifdef CONFIG_LS2080A + u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET; +#endif #ifdef COUNTER_FREQUENCY_REAL unsigned long cntfrq = COUNTER_FREQUENCY_REAL; @@ -650,6 +653,15 @@ int timer_init(void) out_le32(cltbenr, 0xf); #endif +#ifdef CONFIG_LS2080A + /* + * In certain Layerscape SoCs, the clock for each core's + * has an enable bit in the PMU Physical Core Time Base Enable + * Register (PCTBENR), which allows the watchdog to operate. + */ + setbits_le32(pctbenr, 0xff); +#endif + /* Enable clock for timer * This is a global setting. */ |