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| author | Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> | 2016-06-03 18:41:31 +0530 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2016-06-03 14:12:50 -0700 |
| commit | b7f2bbfff6dcc2d5989bb1d20500c431f7927daf (patch) | |
| tree | 4398ed397455de7ea26c78867a1d827b1c95e0dd /arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | |
| parent | ddd8a08052052561af38ecbe30930001a2ae940b (diff) | |
| download | u-boot-imx-b7f2bbfff6dcc2d5989bb1d20500c431f7927daf.zip u-boot-imx-b7f2bbfff6dcc2d5989bb1d20500c431f7927daf.tar.gz u-boot-imx-b7f2bbfff6dcc2d5989bb1d20500c431f7927daf.tar.bz2 | |
armv8: fsl-layerscape: Add support of QorIQ LS1012A SoC
The QorIQ LS1012A processor, optimized for battery-backed or
USB-powered, integrates a single ARM Cortex-A53 core with a hardware
packet forwarding engine and high-speed interfaces to deliver
line-rate networking performance.
This patch add support of LS1012A SoC along with
- Update platform & DDR clock read logic as per SVR
- Define MMDC controller register set.
- Update LUT base address for PCIe
- Avoid L3 platform cache compilation
- Update USB address, errata
- SerDes table
- Added CSU IDs for SDHC2, SAI-1 to SAI-4
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Makarand Pawagi <makarand.pawagi@mindspeed.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S')
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index d743ffe..5af6b73 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -183,6 +183,7 @@ ENTRY(lowlevel_init) ret ENDPROC(lowlevel_init) +#ifdef CONFIG_FSL_LSCH3 hnf_pstate_poll: /* x0 has the desired status, return 0 for success, 1 for timeout * clobber x1, x2, x3, x4, x6, x7 @@ -260,6 +261,7 @@ ENTRY(__asm_flush_l3_cache) mov lr, x29 ret ENDPROC(__asm_flush_l3_cache) +#endif #ifdef CONFIG_MP /* Keep literals not used by the secondary boot code outside it */ |