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| author | Tom Rini <trini@konsulko.com> | 2016-07-26 17:34:28 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2016-07-26 17:34:28 -0400 |
| commit | 9c7a0a600bfc8741e2941ce9bb965f2e77d6bbea (patch) | |
| tree | a475756b966b614ad545299fa82dfd89c863aab8 /arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc | |
| parent | c3c9fd31bad80ead1682de917e27fa6073eae02b (diff) | |
| parent | 8401c7103d73b4010df95bf8bc79a60f378f1e50 (diff) | |
| download | u-boot-imx-9c7a0a600bfc8741e2941ce9bb965f2e77d6bbea.zip u-boot-imx-9c7a0a600bfc8741e2941ce9bb965f2e77d6bbea.tar.gz u-boot-imx-9c7a0a600bfc8741e2941ce9bb965f2e77d6bbea.tar.bz2 | |
Merge git://git.denx.de/u-boot-fsl-qoriq
Diffstat (limited to 'arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc')
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc index 8eee016..f7b949a 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc +++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc @@ -3,6 +3,7 @@ SoC overview 1. LS1043A 2. LS2080A 3. LS1012A + 4. LS1046A LS1043A --------- @@ -127,3 +128,44 @@ The LS1012A SoC includes the following function and features: - Two WatchDog timers - ARM generic timer - QorIQ platform's trust architecture 2.1 + +LS1046A +-------- +The LS1046A integrated multicore processor combines four ARM Cortex-A72 +processor cores with datapath acceleration optimized for L2/3 packet +processing, single pass security offload and robust traffic management +and quality of service. + +The LS1046A SoC includes the following function and features: + - Four 64-bit ARM Cortex-A72 CPUs + - 2 MB unified L2 Cache + - One 64-bit DDR4 SDRAM memory controllers with ECC and interleaving + support + - Data Path Acceleration Architecture (DPAA) incorporating acceleration the + the following functions: + - Packet parsing, classification, and distribution (FMan) + - Queue management for scheduling, packet sequencing, and congestion + management (QMan) + - Hardware buffer management for buffer allocation and de-allocation (BMan) + - Cryptography acceleration (SEC) + - Two Configurable x4 SerDes + - Two PLLs per four-lane SerDes + - Support for 10G operation + - Ethernet interfaces by FMan + - Up to 2 x XFI supporting 10G interface (MAC 9, 10) + - Up to 1 x QSGMII (MAC 5, 6, 10, 1) + - Up to 4 x SGMII supporting 1000Mbps (MAC 5, 6, 9, 10) + - Up to 3 x SGMII supporting 2500Mbps (MAC 5, 9, 10) + - Up to 2 x RGMII supporting 1000Mbps (MAC 3, 4) + - High-speed peripheral interfaces + - Three PCIe 3.0 controllers, one supporting x4 operation + - One serial ATA (SATA 3.0) controllers + - Additional peripheral interfaces + - Three high-speed USB 3.0 controllers with integrated PHY + - Enhanced secure digital host controller (eSDXC/eMMC) + - Quad Serial Peripheral Interface (QSPI) Controller + - Serial peripheral interface (SPI) controller + - Four I2C controllers + - Two DUARTs + - Integrated flash controller (IFC) supporting NAND and NOR flash + - QorIQ platform's trust architecture 2.1 |