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| author | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | 2016-07-18 14:10:37 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2016-07-20 11:13:26 +0200 |
| commit | 55edb9d4d521ff733d217ddf47ad7bf4650676be (patch) | |
| tree | cc956c224537529302518f2c5c45ea3afcdb1e8d /arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3 | |
| parent | 66669fcf809c1e3ff644b12e04e625d3737ffd8e (diff) | |
| download | u-boot-imx-55edb9d4d521ff733d217ddf47ad7bf4650676be.zip u-boot-imx-55edb9d4d521ff733d217ddf47ad7bf4650676be.tar.gz u-boot-imx-55edb9d4d521ff733d217ddf47ad7bf4650676be.tar.bz2 | |
mtd: cfi_flash: fix polling for bit XSR.7 on Intel chips
flash_full_status_check() checks bit XSR.7 on Intel chips. This
should be done by only checking bit 7 and not by comparing the
whole status byte or word with 0x80.
This fixes the non-working block erase in the pflash emulation
of Qemu when used with the MIPS Malta board. MIPS Malta uses x32
mode to access the pflash device. In x32 mode Qemu mirrors the
lower 16 bits of the status word into the upper 16 bits. Thus
the CFI driver gets a status word of 0x8080 in x32 mode. If
flash_full_status_check() uses flash_isequal(), then it polls for
XSR.7 by comparing 0x8080 with 0x80 which never becomes true.
Reported-by: Alon Bar-Lev <alon.barlev@gmail.com>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3')
0 files changed, 0 insertions, 0 deletions