stm32: move stm32 specific code to mach-stm32

This patch moves stm32 sources at one place, with this armv7m now contains
only generic stuff.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>

11 files changed, 0 insertions, 1085 deletions

diff --git a/arch/arm/cpu/armv7m/Makefile b/arch/arm/cpu/armv7m/Makefile
index 93a1956..aff60e8 100644
--- a/arch/arm/cpu/armv7m/Makefile
+++ b/arch/arm/cpu/armv7m/Makefile
@@ -7,6 +7,3 @@
 
 extra-y := start.o
 obj-y += cpu.o
-
-obj-$(CONFIG_STM32F1) += stm32f1/
-obj-$(CONFIG_STM32F4) += stm32f4/
diff --git a/arch/arm/cpu/armv7m/stm32f1/Makefile b/arch/arm/cpu/armv7m/stm32f1/Makefile
deleted file mode 100644
index e2081db..0000000
--- a/arch/arm/cpu/armv7m/stm32f1/Makefile
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2015
-# Kamil Lulko, <kamil.lulko@gmail.com>
-#
-# Copyright 2015 ATS Advanced Telematics Systems GmbH
-# Copyright 2015 Konsulko Group, Matt Porter <mporter@konsulko.com>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y += soc.o clock.o timer.o flash.o
diff --git a/arch/arm/cpu/armv7m/stm32f1/clock.c b/arch/arm/cpu/armv7m/stm32f1/clock.c
deleted file mode 100644
index 2820848..0000000
--- a/arch/arm/cpu/armv7m/stm32f1/clock.c
+++ /dev/null
@@ -1,196 +0,0 @@
-/*
- * (C) Copyright 2015
- * Kamil Lulko, <kamil.lulko@gmail.com>
- *
- * Copyright 2015 ATS Advanced Telematics Systems GmbH
- * Copyright 2015 Konsulko Group, Matt Porter <mporter@konsulko.com>
- *
- * (C) Copyright 2014
- * STMicroelectronics
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/stm32.h>
-
-#define RCC_CR_HSION		(1 << 0)
-#define RCC_CR_HSEON		(1 << 16)
-#define RCC_CR_HSERDY		(1 << 17)
-#define RCC_CR_HSEBYP		(1 << 18)
-#define RCC_CR_CSSON		(1 << 19)
-#define RCC_CR_PLLON		(1 << 24)
-#define RCC_CR_PLLRDY		(1 << 25)
-
-#define RCC_CFGR_PLLMUL_MASK	0x3C0000
-#define RCC_CFGR_PLLMUL_SHIFT	18
-#define RCC_CFGR_PLLSRC_HSE	(1 << 16)
-
-#define RCC_CFGR_AHB_PSC_MASK	0xF0
-#define RCC_CFGR_APB1_PSC_MASK	0x700
-#define RCC_CFGR_APB2_PSC_MASK	0x3800
-#define RCC_CFGR_SW0		(1 << 0)
-#define RCC_CFGR_SW1		(1 << 1)
-#define RCC_CFGR_SW_MASK	0x3
-#define RCC_CFGR_SW_HSI		0
-#define RCC_CFGR_SW_HSE		RCC_CFGR_SW0
-#define RCC_CFGR_SW_PLL		RCC_CFGR_SW1
-#define RCC_CFGR_SWS0		(1 << 2)
-#define RCC_CFGR_SWS1		(1 << 3)
-#define RCC_CFGR_SWS_MASK	0xC
-#define RCC_CFGR_SWS_HSI	0
-#define RCC_CFGR_SWS_HSE	RCC_CFGR_SWS0
-#define RCC_CFGR_SWS_PLL	RCC_CFGR_SWS1
-#define RCC_CFGR_HPRE_SHIFT	4
-#define RCC_CFGR_PPRE1_SHIFT	8
-#define RCC_CFGR_PPRE2_SHIFT	11
-
-#define RCC_APB1ENR_PWREN	(1 << 28)
-
-#define PWR_CR_VOS0		(1 << 14)
-#define PWR_CR_VOS1		(1 << 15)
-#define PWR_CR_VOS_MASK		0xC000
-#define PWR_CR_VOS_SCALE_MODE_1	(PWR_CR_VOS0 | PWR_CR_VOS1)
-#define PWR_CR_VOS_SCALE_MODE_2	(PWR_CR_VOS1)
-#define PWR_CR_VOS_SCALE_MODE_3	(PWR_CR_VOS0)
-
-#define FLASH_ACR_WS(n)		n
-#define FLASH_ACR_PRFTEN	(1 << 8)
-#define FLASH_ACR_ICEN		(1 << 9)
-#define FLASH_ACR_DCEN		(1 << 10)
-
-struct psc {
-	u8	ahb_psc;
-	u8	apb1_psc;
-	u8	apb2_psc;
-};
-
-#define AHB_PSC_1		0
-#define AHB_PSC_2		0x8
-#define AHB_PSC_4		0x9
-#define AHB_PSC_8		0xA
-#define AHB_PSC_16		0xB
-#define AHB_PSC_64		0xC
-#define AHB_PSC_128		0xD
-#define AHB_PSC_256		0xE
-#define AHB_PSC_512		0xF
-
-#define APB_PSC_1		0
-#define APB_PSC_2		0x4
-#define APB_PSC_4		0x5
-#define APB_PSC_8		0x6
-#define APB_PSC_16		0x7
-
-#if !defined(CONFIG_STM32_HSE_HZ)
-#error "CONFIG_STM32_HSE_HZ not defined!"
-#else
-#if (CONFIG_STM32_HSE_HZ == 8000000)
-#define RCC_CFGR_PLLMUL_CFG	0x7
-struct psc psc_hse = {
-	.ahb_psc = AHB_PSC_1,
-	.apb1_psc = APB_PSC_2,
-	.apb2_psc = APB_PSC_1
-};
-#else
-#error "No PLL/Prescaler configuration for given CONFIG_STM32_HSE_HZ exists"
-#endif
-#endif
-
-int configure_clocks(void)
-{
-	/* Reset RCC configuration */
-	setbits_le32(&STM32_RCC->cr, RCC_CR_HSION);
-	writel(0, &STM32_RCC->cfgr); /* Reset CFGR */
-	clrbits_le32(&STM32_RCC->cr, (RCC_CR_HSEON | RCC_CR_CSSON
-		| RCC_CR_PLLON));
-	clrbits_le32(&STM32_RCC->cr, RCC_CR_HSEBYP);
-	writel(0, &STM32_RCC->cir); /* Disable all interrupts */
-
-	/* Configure for HSE+PLL operation */
-	setbits_le32(&STM32_RCC->cr, RCC_CR_HSEON);
-	while (!(readl(&STM32_RCC->cr) & RCC_CR_HSERDY))
-		;
-
-	/* Enable high performance mode, System frequency up to 168 MHz */
-	setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_PWREN);
-	writel(PWR_CR_VOS_SCALE_MODE_1, &STM32_PWR->cr);
-
-	setbits_le32(&STM32_RCC->cfgr,
-		     RCC_CFGR_PLLMUL_CFG << RCC_CFGR_PLLMUL_SHIFT);
-	setbits_le32(&STM32_RCC->cfgr, RCC_CFGR_PLLSRC_HSE);
-	setbits_le32(&STM32_RCC->cfgr, ((
-		psc_hse.ahb_psc << RCC_CFGR_HPRE_SHIFT)
-		| (psc_hse.apb1_psc << RCC_CFGR_PPRE1_SHIFT)
-		| (psc_hse.apb2_psc << RCC_CFGR_PPRE2_SHIFT)));
-
-	setbits_le32(&STM32_RCC->cr, RCC_CR_PLLON);
-
-	while (!(readl(&STM32_RCC->cr) & RCC_CR_PLLRDY))
-		;
-
-	/* 5 wait states, Prefetch enabled, D-Cache enabled, I-Cache enabled */
-	writel(FLASH_ACR_WS(5) | FLASH_ACR_PRFTEN | FLASH_ACR_ICEN
-		| FLASH_ACR_DCEN, &STM32_FLASH->acr);
-
-	clrbits_le32(&STM32_RCC->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1));
-	setbits_le32(&STM32_RCC->cfgr, RCC_CFGR_SW_PLL);
-
-	while ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) !=
-			RCC_CFGR_SWS_PLL)
-		;
-
-	return 0;
-}
-
-unsigned long clock_get(enum clock clck)
-{
-	u32 sysclk = 0;
-	u32 shift = 0;
-	/* PLL table lookups for clock computation */
-	u8 pll_mul_table[16] = {
-		2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16
-	};
-	/* Prescaler table lookups for clock computation */
-	u8 ahb_psc_table[16] = {
-		0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9
-	};
-	u8 apb_psc_table[8] = {
-		0, 0, 0, 0, 1, 2, 3, 4
-	};
-
-	if ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) ==
-			RCC_CFGR_SWS_PLL) {
-		u16 pll;
-		pll = ((readl(&STM32_RCC->cfgr) & RCC_CFGR_PLLMUL_MASK)
-			>> RCC_CFGR_PLLMUL_SHIFT);
-		sysclk = CONFIG_STM32_HSE_HZ * pll_mul_table[pll];
-	}
-
-	switch (clck) {
-	case CLOCK_CORE:
-		return sysclk;
-		break;
-	case CLOCK_AHB:
-		shift = ahb_psc_table[(
-			(readl(&STM32_RCC->cfgr) & RCC_CFGR_AHB_PSC_MASK)
-			>> RCC_CFGR_HPRE_SHIFT)];
-		return sysclk >>= shift;
-		break;
-	case CLOCK_APB1:
-		shift = apb_psc_table[(
-			(readl(&STM32_RCC->cfgr) & RCC_CFGR_APB1_PSC_MASK)
-			>> RCC_CFGR_PPRE1_SHIFT)];
-		return sysclk >>= shift;
-		break;
-	case CLOCK_APB2:
-		shift = apb_psc_table[(
-			(readl(&STM32_RCC->cfgr) & RCC_CFGR_APB2_PSC_MASK)
-			>> RCC_CFGR_PPRE2_SHIFT)];
-		return sysclk >>= shift;
-		break;
-	default:
-		return 0;
-		break;
-	}
-}
diff --git a/arch/arm/cpu/armv7m/stm32f1/flash.c b/arch/arm/cpu/armv7m/stm32f1/flash.c
deleted file mode 100644
index 7d41f63..0000000
--- a/arch/arm/cpu/armv7m/stm32f1/flash.c
+++ /dev/null
@@ -1,180 +0,0 @@
-/*
- * (C) Copyright 2015
- * Kamil Lulko, <kamil.lulko@gmail.com>
- *
- * Copyright 2015 ATS Advanced Telematics Systems GmbH
- * Copyright 2015 Konsulko Group, Matt Porter <mporter@konsulko.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/stm32.h>
-
-#define STM32_FLASH_KEY1	0x45670123
-#define STM32_FLASH_KEY2	0xcdef89ab
-
-#define STM32_NUM_BANKS	2
-#define STM32_MAX_BANK	0x200
-
-flash_info_t flash_info[STM32_NUM_BANKS];
-static struct stm32_flash_bank_regs *flash_bank[STM32_NUM_BANKS];
-
-static void stm32f1_flash_lock(u8 bank, u8 lock)
-{
-	if (lock) {
-		setbits_le32(&flash_bank[bank]->cr, STM32_FLASH_CR_LOCK);
-	} else {
-		writel(STM32_FLASH_KEY1, &flash_bank[bank]->keyr);
-		writel(STM32_FLASH_KEY2, &flash_bank[bank]->keyr);
-	}
-}
-
-/* Only XL devices are supported (2 KiB sector size) */
-unsigned long flash_init(void)
-{
-	u8 i, banks;
-	u16 j, size;
-
-	/* Set up accessors for XL devices with wonky register layout */
-	flash_bank[0] = (struct stm32_flash_bank_regs *)&STM32_FLASH->keyr;
-	flash_bank[1] = (struct stm32_flash_bank_regs *)&STM32_FLASH->keyr2;
-
-	/*
-	 * Get total flash size (in KiB) and configure number of banks
-	 * present and sector count per bank.
-	 */
-	size = readw(&STM32_DES->flash_size);
-	if (size <= STM32_MAX_BANK) {
-		banks = 1;
-		flash_info[0].sector_count = size >> 1;
-	} else if (size > STM32_MAX_BANK) {
-		banks = 2;
-		flash_info[0].sector_count = STM32_MAX_BANK >> 1;
-		flash_info[1].sector_count = (size - STM32_MAX_BANK) >> 1;
-	}
-
-	/* Configure start/size for all sectors */
-	for (i = 0; i < banks; i++) {
-		flash_info[i].flash_id = FLASH_STM32F1;
-		flash_info[i].start[0] = CONFIG_SYS_FLASH_BASE + (i << 19);
-		flash_info[i].size = 2048;
-		for (j = 1; (j < flash_info[i].sector_count); j++) {
-			flash_info[i].start[j] = flash_info[i].start[j - 1]
-				+ 2048;
-			flash_info[i].size += 2048;
-		}
-	}
-
-	return size << 10;
-}
-
-void flash_print_info(flash_info_t *info)
-{
-	int i;
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		printf("Missing or unknown FLASH type\n");
-		return;
-	} else if (info->flash_id == FLASH_STM32F1) {
-		printf("STM32F1 Embedded Flash\n");
-	}
-
-	printf("  Size: %ld MB in %d Sectors\n",
-	       info->size >> 10, info->sector_count);
-
-	printf("  Sector Start Addresses:");
-	for (i = 0; i < info->sector_count; ++i) {
-		if ((i % 5) == 0)
-			printf("\n   ");
-		printf(" %08lX%s",
-		       info->start[i],
-			info->protect[i] ? " (RO)" : "     ");
-	}
-	printf("\n");
-	return;
-}
-
-int flash_erase(flash_info_t *info, int first, int last)
-{
-	u8 bank = 0xff;
-	int i;
-
-	for (i = 0; i < STM32_NUM_BANKS; i++) {
-		if (info == &flash_info[i]) {
-			bank = i;
-			break;
-		}
-	}
-	if (bank == 0xff)
-		return -1;
-
-	stm32f1_flash_lock(bank, 0);
-
-	for (i = first; i <= last; i++) {
-		while (readl(&flash_bank[bank]->sr) & STM32_FLASH_SR_BSY)
-			;
-
-		setbits_le32(&flash_bank[bank]->cr, STM32_FLASH_CR_PER);
-
-		writel(info->start[i], &flash_bank[bank]->ar);
-
-		setbits_le32(&flash_bank[bank]->cr, STM32_FLASH_CR_STRT);
-
-		while (readl(&flash_bank[bank]->sr) & STM32_FLASH_SR_BSY)
-			;
-	}
-
-	clrbits_le32(&flash_bank[bank]->cr, STM32_FLASH_CR_PER);
-
-	stm32f1_flash_lock(bank, 1);
-
-	return 0;
-}
-
-int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
-	ulong i;
-	u8 bank = 0xff;
-
-	if (addr & 1) {
-		printf("Flash address must be half word aligned\n");
-		return -1;
-	}
-
-	if (cnt & 1) {
-		printf("Flash length must be half word aligned\n");
-		return -1;
-	}
-
-	for (i = 0; i < 2; i++) {
-		if (info == &flash_info[i]) {
-			bank = i;
-			break;
-		}
-	}
-
-	if (bank == 0xff)
-		return -1;
-
-	while (readl(&flash_bank[bank]->sr) & STM32_FLASH_SR_BSY)
-		;
-
-	stm32f1_flash_lock(bank, 0);
-
-	setbits_le32(&flash_bank[bank]->cr, STM32_FLASH_CR_PG);
-
-	/* STM32F1 requires half word writes */
-	for (i = 0; i < cnt >> 1; i++) {
-		*(u16 *)(addr + i * 2) = ((u16 *)src)[i];
-		while (readl(&flash_bank[bank]->sr) & STM32_FLASH_SR_BSY)
-			;
-	}
-
-	clrbits_le32(&flash_bank[bank]->cr, STM32_FLASH_CR_PG);
-
-	stm32f1_flash_lock(bank, 1);
-
-	return 0;
-}
diff --git a/arch/arm/cpu/armv7m/stm32f1/soc.c b/arch/arm/cpu/armv7m/stm32f1/soc.c
deleted file mode 100644
index 4438621..0000000
--- a/arch/arm/cpu/armv7m/stm32f1/soc.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * (C) Copyright 2015
- * Kamil Lulko, <kamil.lulko@gmail.com>
- *
- * Copyright 2015 ATS Advanced Telematics Systems GmbH
- * Copyright 2015 Konsulko Group, Matt Porter <mporter@konsulko.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/armv7m.h>
-#include <asm/arch/stm32.h>
-
-u32 get_cpu_rev(void)
-{
-	return 0;
-}
-
-int arch_cpu_init(void)
-{
-	configure_clocks();
-
-	/*
-	 * Configure the memory protection unit (MPU) to allow full access to
-	 * the whole 4GB address space.
-	 */
-	writel(0, &V7M_MPU->rnr);
-	writel(0, &V7M_MPU->rbar);
-	writel((V7M_MPU_RASR_AP_RW_RW | V7M_MPU_RASR_SIZE_4GB
-		| V7M_MPU_RASR_EN), &V7M_MPU->rasr);
-	writel(V7M_MPU_CTRL_ENABLE | V7M_MPU_CTRL_HFNMIENA, &V7M_MPU->ctrl);
-
-	return 0;
-}
diff --git a/arch/arm/cpu/armv7m/stm32f1/timer.c b/arch/arm/cpu/armv7m/stm32f1/timer.c
deleted file mode 100644
index 6a26198..0000000
--- a/arch/arm/cpu/armv7m/stm32f1/timer.c
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- * (C) Copyright 2015
- * Kamil Lulko, <kamil.lulko@gmail.com>
- *
- * Copyright 2015 ATS Advanced Telematics Systems GmbH
- * Copyright 2015 Konsulko Group, Matt Porter <mporter@konsulko.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/armv7m.h>
-#include <asm/arch/stm32.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define STM32_TIM2_BASE	(STM32_APB1PERIPH_BASE + 0x0000)
-
-#define RCC_APB1ENR_TIM2EN	(1 << 0)
-
-struct stm32_tim2_5 {
-	u32 cr1;
-	u32 cr2;
-	u32 smcr;
-	u32 dier;
-	u32 sr;
-	u32 egr;
-	u32 ccmr1;
-	u32 ccmr2;
-	u32 ccer;
-	u32 cnt;
-	u32 psc;
-	u32 arr;
-	u32 reserved1;
-	u32 ccr1;
-	u32 ccr2;
-	u32 ccr3;
-	u32 ccr4;
-	u32 reserved2;
-	u32 dcr;
-	u32 dmar;
-	u32 or;
-};
-
-#define TIM_CR1_CEN	(1 << 0)
-
-#define TIM_EGR_UG	(1 << 0)
-
-int timer_init(void)
-{
-	struct stm32_tim2_5 *tim = (struct stm32_tim2_5 *)STM32_TIM2_BASE;
-
-	setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_TIM2EN);
-
-	if (clock_get(CLOCK_AHB) == clock_get(CLOCK_APB1))
-		writel((clock_get(CLOCK_APB1) / CONFIG_SYS_HZ_CLOCK) - 1,
-		       &tim->psc);
-	else
-		writel(((clock_get(CLOCK_APB1) * 2) / CONFIG_SYS_HZ_CLOCK) - 1,
-		       &tim->psc);
-
-	writel(0xFFFFFFFF, &tim->arr);
-	writel(TIM_CR1_CEN, &tim->cr1);
-	setbits_le32(&tim->egr, TIM_EGR_UG);
-
-	gd->arch.tbl = 0;
-	gd->arch.tbu = 0;
-	gd->arch.lastinc = 0;
-
-	return 0;
-}
-
-ulong get_timer(ulong base)
-{
-	return (get_ticks() / (CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ)) - base;
-}
-
-unsigned long long get_ticks(void)
-{
-	struct stm32_tim2_5 *tim = (struct stm32_tim2_5 *)STM32_TIM2_BASE;
-	u32 now;
-
-	now = readl(&tim->cnt);
-
-	if (now >= gd->arch.lastinc)
-		gd->arch.tbl += (now - gd->arch.lastinc);
-	else
-		gd->arch.tbl += (0xFFFFFFFF - gd->arch.lastinc) + now;
-
-	gd->arch.lastinc = now;
-
-	return gd->arch.tbl;
-}
-
-void reset_timer(void)
-{
-	struct stm32_tim2_5 *tim = (struct stm32_tim2_5 *)STM32_TIM2_BASE;
-
-	gd->arch.lastinc = readl(&tim->cnt);
-	gd->arch.tbl = 0;
-}
-
-/* delay x useconds */
-void __udelay(ulong usec)
-{
-	unsigned long long start;
-
-	start = get_ticks();		/* get current timestamp */
-	while ((get_ticks() - start) < usec)
-		;			/* loop till time has passed */
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
-	return CONFIG_SYS_HZ_CLOCK;
-}
diff --git a/arch/arm/cpu/armv7m/stm32f4/Makefile b/arch/arm/cpu/armv7m/stm32f4/Makefile
deleted file mode 100644
index 42d01db..0000000
--- a/arch/arm/cpu/armv7m/stm32f4/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2015
-# Kamil Lulko, <kamil.lulko@gmail.com>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y += soc.o clock.o timer.o flash.o
diff --git a/arch/arm/cpu/armv7m/stm32f4/clock.c b/arch/arm/cpu/armv7m/stm32f4/clock.c
deleted file mode 100644
index 3deb17a..0000000
--- a/arch/arm/cpu/armv7m/stm32f4/clock.c
+++ /dev/null
@@ -1,223 +0,0 @@
-/*
- * (C) Copyright 2015
- * Kamil Lulko, <kamil.lulko@gmail.com>
- *
- * (C) Copyright 2014
- * STMicroelectronics
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/stm32.h>
-
-#define RCC_CR_HSION		(1 << 0)
-#define RCC_CR_HSEON		(1 << 16)
-#define RCC_CR_HSERDY		(1 << 17)
-#define RCC_CR_HSEBYP		(1 << 18)
-#define RCC_CR_CSSON		(1 << 19)
-#define RCC_CR_PLLON		(1 << 24)
-#define RCC_CR_PLLRDY		(1 << 25)
-
-#define RCC_PLLCFGR_PLLM_MASK	0x3F
-#define RCC_PLLCFGR_PLLN_MASK	0x7FC0
-#define RCC_PLLCFGR_PLLP_MASK	0x30000
-#define RCC_PLLCFGR_PLLQ_MASK	0xF000000
-#define RCC_PLLCFGR_PLLSRC	(1 << 22)
-#define RCC_PLLCFGR_PLLN_SHIFT	6
-#define RCC_PLLCFGR_PLLP_SHIFT	16
-#define RCC_PLLCFGR_PLLQ_SHIFT	24
-
-#define RCC_CFGR_AHB_PSC_MASK	0xF0
-#define RCC_CFGR_APB1_PSC_MASK	0x1C00
-#define RCC_CFGR_APB2_PSC_MASK	0xE000
-#define RCC_CFGR_SW0		(1 << 0)
-#define RCC_CFGR_SW1		(1 << 1)
-#define RCC_CFGR_SW_MASK	0x3
-#define RCC_CFGR_SW_HSI		0
-#define RCC_CFGR_SW_HSE		RCC_CFGR_SW0
-#define RCC_CFGR_SW_PLL		RCC_CFGR_SW1
-#define RCC_CFGR_SWS0		(1 << 2)
-#define RCC_CFGR_SWS1		(1 << 3)
-#define RCC_CFGR_SWS_MASK	0xC
-#define RCC_CFGR_SWS_HSI	0
-#define RCC_CFGR_SWS_HSE	RCC_CFGR_SWS0
-#define RCC_CFGR_SWS_PLL	RCC_CFGR_SWS1
-#define RCC_CFGR_HPRE_SHIFT	4
-#define RCC_CFGR_PPRE1_SHIFT	10
-#define RCC_CFGR_PPRE2_SHIFT	13
-
-#define RCC_APB1ENR_PWREN	(1 << 28)
-
-#define PWR_CR_VOS0		(1 << 14)
-#define PWR_CR_VOS1		(1 << 15)
-#define PWR_CR_VOS_MASK		0xC000
-#define PWR_CR_VOS_SCALE_MODE_1	(PWR_CR_VOS0 | PWR_CR_VOS1)
-#define PWR_CR_VOS_SCALE_MODE_2	(PWR_CR_VOS1)
-#define PWR_CR_VOS_SCALE_MODE_3	(PWR_CR_VOS0)
-
-#define FLASH_ACR_WS(n)		n
-#define FLASH_ACR_PRFTEN	(1 << 8)
-#define FLASH_ACR_ICEN		(1 << 9)
-#define FLASH_ACR_DCEN		(1 << 10)
-
-struct pll_psc {
-	u8	pll_m;
-	u16	pll_n;
-	u8	pll_p;
-	u8	pll_q;
-	u8	ahb_psc;
-	u8	apb1_psc;
-	u8	apb2_psc;
-};
-
-#define AHB_PSC_1		0
-#define AHB_PSC_2		0x8
-#define AHB_PSC_4		0x9
-#define AHB_PSC_8		0xA
-#define AHB_PSC_16		0xB
-#define AHB_PSC_64		0xC
-#define AHB_PSC_128		0xD
-#define AHB_PSC_256		0xE
-#define AHB_PSC_512		0xF
-
-#define APB_PSC_1		0
-#define APB_PSC_2		0x4
-#define APB_PSC_4		0x5
-#define APB_PSC_8		0x6
-#define APB_PSC_16		0x7
-
-#if !defined(CONFIG_STM32_HSE_HZ)
-#error "CONFIG_STM32_HSE_HZ not defined!"
-#else
-#if (CONFIG_STM32_HSE_HZ == 8000000)
-#if (CONFIG_SYS_CLK_FREQ == 180000000)
-/* 180 MHz */
-struct pll_psc sys_pll_psc = {
-	.pll_m = 8,
-	.pll_n = 360,
-	.pll_p = 2,
-	.pll_q = 8,
-	.ahb_psc = AHB_PSC_1,
-	.apb1_psc = APB_PSC_4,
-	.apb2_psc = APB_PSC_2
-};
-#else
-/* default 168 MHz */
-struct pll_psc sys_pll_psc = {
-	.pll_m = 8,
-	.pll_n = 336,
-	.pll_p = 2,
-	.pll_q = 7,
-	.ahb_psc = AHB_PSC_1,
-	.apb1_psc = APB_PSC_4,
-	.apb2_psc = APB_PSC_2
-};
-#endif
-#else
-#error "No PLL/Prescaler configuration for given CONFIG_STM32_HSE_HZ exists"
-#endif
-#endif
-
-int configure_clocks(void)
-{
-	/* Reset RCC configuration */
-	setbits_le32(&STM32_RCC->cr, RCC_CR_HSION);
-	writel(0, &STM32_RCC->cfgr); /* Reset CFGR */
-	clrbits_le32(&STM32_RCC->cr, (RCC_CR_HSEON | RCC_CR_CSSON
-		| RCC_CR_PLLON));
-	writel(0x24003010, &STM32_RCC->pllcfgr); /* Reset value from RM */
-	clrbits_le32(&STM32_RCC->cr, RCC_CR_HSEBYP);
-	writel(0, &STM32_RCC->cir); /* Disable all interrupts */
-
-	/* Configure for HSE+PLL operation */
-	setbits_le32(&STM32_RCC->cr, RCC_CR_HSEON);
-	while (!(readl(&STM32_RCC->cr) & RCC_CR_HSERDY))
-		;
-
-	/* Enable high performance mode, System frequency up to 180 MHz */
-	setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_PWREN);
-	writel(PWR_CR_VOS_SCALE_MODE_1, &STM32_PWR->cr);
-
-	setbits_le32(&STM32_RCC->cfgr, ((
-		sys_pll_psc.ahb_psc << RCC_CFGR_HPRE_SHIFT)
-		| (sys_pll_psc.apb1_psc << RCC_CFGR_PPRE1_SHIFT)
-		| (sys_pll_psc.apb2_psc << RCC_CFGR_PPRE2_SHIFT)));
-
-	writel(sys_pll_psc.pll_m
-		| (sys_pll_psc.pll_n << RCC_PLLCFGR_PLLN_SHIFT)
-		| (((sys_pll_psc.pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT)
-		| (sys_pll_psc.pll_q << RCC_PLLCFGR_PLLQ_SHIFT),
-		&STM32_RCC->pllcfgr);
-	setbits_le32(&STM32_RCC->pllcfgr, RCC_PLLCFGR_PLLSRC);
-
-	setbits_le32(&STM32_RCC->cr, RCC_CR_PLLON);
-
-	while (!(readl(&STM32_RCC->cr) & RCC_CR_PLLRDY))
-		;
-
-	/* 5 wait states, Prefetch enabled, D-Cache enabled, I-Cache enabled */
-	writel(FLASH_ACR_WS(5) | FLASH_ACR_PRFTEN | FLASH_ACR_ICEN
-		| FLASH_ACR_DCEN, &STM32_FLASH->acr);
-
-	clrbits_le32(&STM32_RCC->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1));
-	setbits_le32(&STM32_RCC->cfgr, RCC_CFGR_SW_PLL);
-
-	while ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) !=
-			RCC_CFGR_SWS_PLL)
-		;
-
-	return 0;
-}
-
-unsigned long clock_get(enum clock clck)
-{
-	u32 sysclk = 0;
-	u32 shift = 0;
-	/* Prescaler table lookups for clock computation */
-	u8 ahb_psc_table[16] = {
-		0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9
-	};
-	u8 apb_psc_table[8] = {
-		0, 0, 0, 0, 1, 2, 3, 4
-	};
-
-	if ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) ==
-			RCC_CFGR_SWS_PLL) {
-		u16 pllm, plln, pllp;
-		pllm = (readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
-		plln = ((readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLN_MASK)
-			>> RCC_PLLCFGR_PLLN_SHIFT);
-		pllp = ((((readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLP_MASK)
-			>> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1);
-		sysclk = ((CONFIG_STM32_HSE_HZ / pllm) * plln) / pllp;
-	}
-
-	switch (clck) {
-	case CLOCK_CORE:
-		return sysclk;
-		break;
-	case CLOCK_AHB:
-		shift = ahb_psc_table[(
-			(readl(&STM32_RCC->cfgr) & RCC_CFGR_AHB_PSC_MASK)
-			>> RCC_CFGR_HPRE_SHIFT)];
-		return sysclk >>= shift;
-		break;
-	case CLOCK_APB1:
-		shift = apb_psc_table[(
-			(readl(&STM32_RCC->cfgr) & RCC_CFGR_APB1_PSC_MASK)
-			>> RCC_CFGR_PPRE1_SHIFT)];
-		return sysclk >>= shift;
-		break;
-	case CLOCK_APB2:
-		shift = apb_psc_table[(
-			(readl(&STM32_RCC->cfgr) & RCC_CFGR_APB2_PSC_MASK)
-			>> RCC_CFGR_PPRE2_SHIFT)];
-		return sysclk >>= shift;
-		break;
-	default:
-		return 0;
-		break;
-	}
-}
diff --git a/arch/arm/cpu/armv7m/stm32f4/flash.c b/arch/arm/cpu/armv7m/stm32f4/flash.c
deleted file mode 100644
index a379f47..0000000
--- a/arch/arm/cpu/armv7m/stm32f4/flash.c
+++ /dev/null
@@ -1,146 +0,0 @@
-/*
- * (C) Copyright 2015
- * Kamil Lulko, <kamil.lulko@gmail.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/stm32.h>
-
-#define STM32_FLASH_KEY1	0x45670123
-#define STM32_FLASH_KEY2	0xCDEF89AB
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-
-const u32 sect_sz_kb[CONFIG_SYS_MAX_FLASH_SECT] = {
-	[0 ... 3] =	16 * 1024,
-	[4] =		64 * 1024,
-	[5 ... 11] =	128 * 1024
-};
-
-static void stm32f4_flash_lock(u8 lock)
-{
-	if (lock) {
-		setbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_LOCK);
-	} else {
-		writel(STM32_FLASH_KEY1, &STM32_FLASH->key);
-		writel(STM32_FLASH_KEY2, &STM32_FLASH->key);
-	}
-}
-
-unsigned long flash_init(void)
-{
-	unsigned long total_size = 0;
-	u8 i, j;
-
-	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
-		flash_info[i].flash_id = FLASH_STM32F4;
-		flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
-		flash_info[i].start[0] = CONFIG_SYS_FLASH_BASE + (i << 20);
-		flash_info[i].size = sect_sz_kb[0];
-		for (j = 1; j < CONFIG_SYS_MAX_FLASH_SECT; j++) {
-			flash_info[i].start[j] = flash_info[i].start[j - 1]
-				+ (sect_sz_kb[j - 1]);
-			flash_info[i].size += sect_sz_kb[j];
-		}
-		total_size += flash_info[i].size;
-	}
-
-	return total_size;
-}
-
-void flash_print_info(flash_info_t *info)
-{
-	int i;
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		printf("missing or unknown FLASH type\n");
-		return;
-	} else if (info->flash_id == FLASH_STM32F4) {
-		printf("STM32F4 Embedded Flash\n");
-	}
-
-	printf("  Size: %ld MB in %d Sectors\n",
-	       info->size >> 20, info->sector_count);
-
-	printf("  Sector Start Addresses:");
-	for (i = 0; i < info->sector_count; ++i) {
-		if ((i % 5) == 0)
-			printf("\n   ");
-		printf(" %08lX%s",
-		       info->start[i],
-			info->protect[i] ? " (RO)" : "     ");
-	}
-	printf("\n");
-	return;
-}
-
-int flash_erase(flash_info_t *info, int first, int last)
-{
-	u8 bank = 0xFF;
-	int i;
-
-	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
-		if (info == &flash_info[i]) {
-			bank = i;
-			break;
-		}
-	}
-	if (bank == 0xFF)
-		return -1;
-
-	stm32f4_flash_lock(0);
-
-	for (i = first; i <= last; i++) {
-		while (readl(&STM32_FLASH->sr) & STM32_FLASH_SR_BSY)
-			;
-
-		/* clear old sector number before writing a new one */
-		clrbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_SNB_MASK);
-
-		if (bank == 0) {
-			setbits_le32(&STM32_FLASH->cr,
-				     (i << STM32_FLASH_CR_SNB_OFFSET));
-		} else if (bank == 1) {
-			setbits_le32(&STM32_FLASH->cr,
-				     ((0x10 | i) << STM32_FLASH_CR_SNB_OFFSET));
-		} else {
-			stm32f4_flash_lock(1);
-			return -1;
-		}
-		setbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_SER);
-		setbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_STRT);
-
-		while (readl(&STM32_FLASH->sr) & STM32_FLASH_SR_BSY)
-			;
-
-		clrbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_SER);
-	}
-
-	stm32f4_flash_lock(1);
-	return 0;
-}
-
-int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
-	ulong i;
-
-	while (readl(&STM32_FLASH->sr) & STM32_FLASH_SR_BSY)
-		;
-
-	stm32f4_flash_lock(0);
-
-	setbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_PG);
-	/* To make things simple use byte writes only */
-	for (i = 0; i < cnt; i++) {
-		*(uchar *)(addr + i) = src[i];
-		while (readl(&STM32_FLASH->sr) & STM32_FLASH_SR_BSY)
-			;
-	}
-	clrbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_PG);
-	stm32f4_flash_lock(1);
-
-	return 0;
-}
diff --git a/arch/arm/cpu/armv7m/stm32f4/soc.c b/arch/arm/cpu/armv7m/stm32f4/soc.c
deleted file mode 100644
index b5d06db..0000000
--- a/arch/arm/cpu/armv7m/stm32f4/soc.c
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * (C) Copyright 2015
- * Kamil Lulko, <kamil.lulko@gmail.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/armv7m.h>
-#include <asm/arch/stm32.h>
-
-u32 get_cpu_rev(void)
-{
-	return 0;
-}
-
-int arch_cpu_init(void)
-{
-	configure_clocks();
-
-	/*
-	 * Configure the memory protection unit (MPU) to allow full access to
-	 * the whole 4GB address space.
-	 */
-	writel(0, &V7M_MPU->rnr);
-	writel(0, &V7M_MPU->rbar);
-	writel((V7M_MPU_RASR_AP_RW_RW | V7M_MPU_RASR_SIZE_4GB
-		| V7M_MPU_RASR_EN), &V7M_MPU->rasr);
-	writel(V7M_MPU_CTRL_ENABLE | V7M_MPU_CTRL_HFNMIENA, &V7M_MPU->ctrl);
-
-	return 0;
-}
-
-void s_init(void)
-{
-}
diff --git a/arch/arm/cpu/armv7m/stm32f4/timer.c b/arch/arm/cpu/armv7m/stm32f4/timer.c
deleted file mode 100644
index 1dee190..0000000
--- a/arch/arm/cpu/armv7m/stm32f4/timer.c
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * (C) Copyright 2015
- * Kamil Lulko, <kamil.lulko@gmail.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/armv7m.h>
-#include <asm/arch/stm32.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define STM32_TIM2_BASE	(STM32_APB1PERIPH_BASE + 0x0000)
-
-#define RCC_APB1ENR_TIM2EN	(1 << 0)
-
-struct stm32_tim2_5 {
-	u32 cr1;
-	u32 cr2;
-	u32 smcr;
-	u32 dier;
-	u32 sr;
-	u32 egr;
-	u32 ccmr1;
-	u32 ccmr2;
-	u32 ccer;
-	u32 cnt;
-	u32 psc;
-	u32 arr;
-	u32 reserved1;
-	u32 ccr1;
-	u32 ccr2;
-	u32 ccr3;
-	u32 ccr4;
-	u32 reserved2;
-	u32 dcr;
-	u32 dmar;
-	u32 or;
-};
-
-#define TIM_CR1_CEN	(1 << 0)
-
-#define TIM_EGR_UG	(1 << 0)
-
-int timer_init(void)
-{
-	struct stm32_tim2_5 *tim = (struct stm32_tim2_5 *)STM32_TIM2_BASE;
-
-	setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_TIM2EN);
-
-	if (clock_get(CLOCK_AHB) == clock_get(CLOCK_APB1))
-		writel((clock_get(CLOCK_APB1) / CONFIG_SYS_HZ_CLOCK) - 1,
-		       &tim->psc);
-	else
-		writel(((clock_get(CLOCK_APB1) * 2) / CONFIG_SYS_HZ_CLOCK) - 1,
-		       &tim->psc);
-
-	writel(0xFFFFFFFF, &tim->arr);
-	writel(TIM_CR1_CEN, &tim->cr1);
-	setbits_le32(&tim->egr, TIM_EGR_UG);
-
-	gd->arch.tbl = 0;
-	gd->arch.tbu = 0;
-	gd->arch.lastinc = 0;
-
-	return 0;
-}
-
-ulong get_timer(ulong base)
-{
-	return (get_ticks() / (CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ)) - base;
-}
-
-unsigned long long get_ticks(void)
-{
-	struct stm32_tim2_5 *tim = (struct stm32_tim2_5 *)STM32_TIM2_BASE;
-	u32 now;
-
-	now = readl(&tim->cnt);
-
-	if (now >= gd->arch.lastinc)
-		gd->arch.tbl += (now - gd->arch.lastinc);
-	else
-		gd->arch.tbl += (0xFFFFFFFF - gd->arch.lastinc) + now;
-
-	gd->arch.lastinc = now;
-
-	return gd->arch.tbl;
-}
-
-void reset_timer(void)
-{
-	struct stm32_tim2_5 *tim = (struct stm32_tim2_5 *)STM32_TIM2_BASE;
-
-	gd->arch.lastinc = readl(&tim->cnt);
-	gd->arch.tbl = 0;
-}
-
-/* delay x useconds */
-void __udelay(ulong usec)
-{
-	unsigned long long start;
-
-	start = get_ticks();		/* get current timestamp */
-	while ((get_ticks() - start) < usec)
-		;			/* loop till time has passed */
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
-	return CONFIG_SYS_HZ_CLOCK;
-}