OMAP5: emif/ddr: Change emif settings as required for ES1.0 silicon.

The OMAP5 silicon has new DDR PHY design, which includes a external PHY
as well. So configuring the ext PHY parameters here. Also the EMIF timimg
registers and a couple of DDR mode registers needs to be updated based on
the testing from the actual silicon.

Signed-off-by: R Sricharan <r.sricharan@ti.com>

4 files changed, 118 insertions, 26 deletions

diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c
index a183c34..e96a430 100644
--- a/arch/arm/cpu/armv7/omap-common/clocks-common.c
+++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c
@@ -459,6 +459,7 @@ void freq_update_core(void)
 {
 	u32 freq_config1 = 0;
 	const struct dpll_params *core_dpll_params;
+	u32 omap_rev = omap_revision();
 
 	core_dpll_params = get_core_dpll_params();
 	/* Put EMIF clock domain in sw wakeup mode */
@@ -484,11 +485,18 @@ void freq_update_core(void)
 		hang();
 	}
 
-	/* Put EMIF clock domain back in hw auto mode */
-	enable_clock_domain(&prcm->cm_memif_clkstctrl,
-				CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
-	wait_for_clk_enable(&prcm->cm_memif_emif_1_clkctrl);
-	wait_for_clk_enable(&prcm->cm_memif_emif_2_clkctrl);
+	/*
+	 * Putting EMIF in HW_AUTO is seen to be causing issues with
+	 * EMIF clocks and the master DLL. Put EMIF in SW_WKUP
+	 * in OMAP5430 ES1.0 silicon
+	 */
+	if (omap_rev != OMAP5430_ES1_0) {
+		/* Put EMIF clock domain back in hw auto mode */
+		enable_clock_domain(&prcm->cm_memif_clkstctrl,
+					CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
+		wait_for_clk_enable(&prcm->cm_memif_emif_1_clkctrl);
+		wait_for_clk_enable(&prcm->cm_memif_emif_2_clkctrl);
+	}
 }
 
 void bypass_dpll(u32 *const base)
diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c
index 62678ff..db509c9 100644
--- a/arch/arm/cpu/armv7/omap-common/emif-common.c
+++ b/arch/arm/cpu/armv7/omap-common/emif-common.c
@@ -90,20 +90,33 @@ static void do_lpddr2_init(u32 base, u32 cs)
 	 * tZQINIT = 1 us
 	 * Enough loops assuming a maximum of 2GHz
 	 */
+
 	sdelay(2000);
-	set_mr(base, cs, LPDDR2_MR1, MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3);
+
+	if (omap_revision() >= OMAP5430_ES1_0)
+		set_mr(base, cs, LPDDR2_MR1, MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8);
+	else
+		set_mr(base, cs, LPDDR2_MR1, MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3);
+
 	set_mr(base, cs, LPDDR2_MR16, MR16_REF_FULL_ARRAY);
+
 	/*
 	 * Enable refresh along with writing MR2
 	 * Encoding of RL in MR2 is (RL - 2)
 	 */
 	mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK;
 	set_mr(base, cs, mr_addr, RL_FINAL - 2);
+
+	if (omap_revision() >= OMAP5430_ES1_0)
+		set_mr(base, cs, LPDDR2_MR3, 0x1);
 }
 
 static void lpddr2_init(u32 base, const struct emif_regs *regs)
 {
 	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+	u32 *ext_phy_ctrl_base = 0;
+	u32 *emif_ext_phy_ctrl_base = 0;
+	u32 i = 0;
 
 	/* Not NVM */
 	clrbits_le32(&emif->emif_lpddr2_nvm_config, EMIF_REG_CS1NVMEN_MASK);
@@ -119,7 +132,31 @@ static void lpddr2_init(u32 base, const struct emif_regs *regs)
 	 * un-locked frequency & default RL
 	 */
 	writel(regs->sdram_config_init, &emif->emif_sdram_config);
-	writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
+	writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
+
+	ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1);
+	emif_ext_phy_ctrl_base = (u32 *) &(emif->emif_ddr_ext_phy_ctrl_1);
+
+	if (omap_revision() >= OMAP5430_ES1_0) {
+		/* Configure external phy control timing registers */
+		for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
+			writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
+			/* Update shadow registers */
+			writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
+		}
+
+		/*
+		 * external phy 6-24 registers do not change with
+		 * ddr frequency
+		 */
+		for (i = 0; i < EMIF_EXT_PHY_CTRL_CONST_REG; i++) {
+			writel(ext_phy_ctrl_const_base[i],
+						emif_ext_phy_ctrl_base++);
+			/* Update shadow registers */
+			writel(ext_phy_ctrl_const_base[i],
+						emif_ext_phy_ctrl_base++);
+		}
+	}
 
 	do_lpddr2_init(base, CS0);
 	if (regs->sdram_config & EMIF_REG_EBANK_MASK)
diff --git a/arch/arm/cpu/armv7/omap4/sdram_elpida.c b/arch/arm/cpu/armv7/omap4/sdram_elpida.c
index a5ec7d3..b538960 100644
--- a/arch/arm/cpu/armv7/omap4/sdram_elpida.c
+++ b/arch/arm/cpu/armv7/omap4/sdram_elpida.c
@@ -89,6 +89,10 @@ const struct emif_regs emif_regs_elpida_400_mhz_2cs = {
 	.emif_ddr_phy_ctlr_1_init	= 0x049ffff5,
 	.emif_ddr_phy_ctlr_1		= 0x049ff418
 };
+
+/* Dummy registers for OMAP44xx */
+const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG];
+
 const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = {
 	.dmm_lisa_map_0 = 0xFF020100,
 	.dmm_lisa_map_1 = 0,
diff --git a/arch/arm/cpu/armv7/omap5/sdram_elpida.c b/arch/arm/cpu/armv7/omap5/sdram_elpida.c
index ad198e6..85805b8 100644
--- a/arch/arm/cpu/armv7/omap5/sdram_elpida.c
+++ b/arch/arm/cpu/armv7/omap5/sdram_elpida.c
@@ -48,31 +48,76 @@
  */
 
 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
-
-const struct emif_regs emif_regs_elpida_532_mhz_1cs = {
-	.sdram_config_init		= 0x80801aB2,
-	.sdram_config			= 0x808022B2,
+const struct emif_regs emif_regs_elpida_532_mhz_2cs = {
+	.sdram_config_init		= 0x80800EBA,
+	.sdram_config			= 0x808022BA,
 	.ref_ctrl			= 0x0000081A,
 	.sdram_tim1			= 0x772F6873,
-	.sdram_tim2			= 0x304A129A,
-	.sdram_tim3			= 0x02F7E45F,
+	.sdram_tim2			= 0x304a129a,
+	.sdram_tim3			= 0x02f7e45f,
+	.read_idle_ctrl			= 0x00050000,
+	.zq_config			= 0x000b3215,
+	.temp_alert_config		= 0x08000a05,
+	.emif_ddr_phy_ctlr_1_init	= 0x0E28420d,
+	.emif_ddr_phy_ctlr_1		= 0x0E28420d,
+	.emif_ddr_ext_phy_ctrl_1	= 0x04020080,
+	.emif_ddr_ext_phy_ctrl_2	= 0x28C518A3,
+	.emif_ddr_ext_phy_ctrl_3	= 0x518A3146,
+	.emif_ddr_ext_phy_ctrl_4	= 0x0014628C,
+	.emif_ddr_ext_phy_ctrl_5	= 0x04010040
+};
+
+const struct emif_regs emif_regs_elpida_266_mhz_2cs = {
+	.sdram_config_init		= 0x80800EBA,
+	.sdram_config			= 0x808022BA,
+	.ref_ctrl			= 0x0000040D,
+	.sdram_tim1			= 0x2A86B419,
+	.sdram_tim2			= 0x1025094A,
+	.sdram_tim3			= 0x026BA22F,
 	.read_idle_ctrl			= 0x00050000,
-	.zq_config			= 0x000B3215,
-	.temp_alert_config		= 0x08000A05,
-	.emif_ddr_phy_ctlr_1_init	= 0x0E38200D,
-	.emif_ddr_phy_ctlr_1		= 0x0E38200D
+	.zq_config			= 0x000b3215,
+	.temp_alert_config		= 0x08000a05,
+	.emif_ddr_phy_ctlr_1_init	= 0x0E28420d,
+	.emif_ddr_phy_ctlr_1		= 0x0E28420d,
+	.emif_ddr_ext_phy_ctrl_1	= 0x04020080,
+	.emif_ddr_ext_phy_ctrl_2	= 0x0A414829,
+	.emif_ddr_ext_phy_ctrl_3	= 0x14829052,
+	.emif_ddr_ext_phy_ctrl_4	= 0x000520A4,
+	.emif_ddr_ext_phy_ctrl_5	= 0x04010040
 };
 
-const struct dmm_lisa_map_regs lisa_map_4G_x_1_x_2 = {
-	.dmm_lisa_map_0 = 0xFF020100,
+const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = {
+	.dmm_lisa_map_0 = 0x0,
 	.dmm_lisa_map_1 = 0,
 	.dmm_lisa_map_2 = 0,
-	.dmm_lisa_map_3 = 0x80640300
+	.dmm_lisa_map_3 = 0x80740300
+};
+
+const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = {
+	0x01004010,
+	0x00001004,
+	0x04010040,
+	0x01004010,
+	0x00001004,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x80080080,
+	0x00800800,
+	0x08102040,
+	0x00000001,
+	0x540A8150,
+	0xA81502a0,
+	0x002A0540,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000077
 };
 
 static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
 {
-	*regs = &emif_regs_elpida_532_mhz_1cs;
+	*regs = &emif_regs_elpida_532_mhz_2cs;
 }
 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
 	__attribute__((weak, alias("emif_get_reg_dump_sdp")));
@@ -80,7 +125,7 @@ void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
 static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
 						**dmm_lisa_regs)
 {
-	*dmm_lisa_regs = &lisa_map_4G_x_1_x_2;
+	*dmm_lisa_regs = &lisa_map_4G_x_2_x_2;
 }
 
 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
@@ -101,9 +146,7 @@ static void emif_get_device_details_sdp(u32 emif_nr,
 {
 	/* EMIF1 & EMIF2 have identical configuration */
 	*cs0_device_details = elpida_4G_S4_details;
-
-	/* Nothing is conected on cs1 */
-	cs1_device_details = NULL;
+	*cs1_device_details = elpida_4G_S4_details;
 }
 
 void emif_get_device_details(u32 emif_nr,
@@ -167,7 +210,7 @@ void emif_get_device_timings_sdp(u32 emif_nr,
 {
 	/* Identical devices on EMIF1 & EMIF2 */
 	*cs0_device_timings = &elpida_4G_S4_timings;
-	*cs1_device_timings = NULL;
+	*cs1_device_timings = &elpida_4G_S4_timings;
 }
 
 void emif_get_device_timings(u32 emif_nr,