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| author | Jason Liu <jason.hui@linaro.org> | 2012-01-10 00:52:59 +0000 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2012-01-16 08:40:10 +0100 |
| commit | f2f7745825ee5f6bae5b480c8e9c6641a7ffa73b (patch) | |
| tree | d17724b20a301e65ae45fc96049dc5b1dfc09fc6 /arch/arm/cpu/armv7 | |
| parent | 8db9eff6c51ad874d6dadfee70c23302c08bd9c4 (diff) | |
| download | u-boot-imx-f2f7745825ee5f6bae5b480c8e9c6641a7ffa73b.zip u-boot-imx-f2f7745825ee5f6bae5b480c8e9c6641a7ffa73b.tar.gz u-boot-imx-f2f7745825ee5f6bae5b480c8e9c6641a7ffa73b.tar.bz2 | |
imx: mx6q: add aipstz init for off platform periph
Init peripheral access control register of AIPSTZ OPACRx:
Buffer Writes(BW): 0 -> not bufferable,
Supervisor Protect(SP): 0 -> not require supervisor privilege level for accesses.
Write Protect(WP): 0 -> allows write accesses.
Trusted Protect(TP): 0 -> allows unstrusted master
Signed-off-by: Jason Liu <jason.hui@linaro.org>
Cc: Stefano Babic <sbabic@denx.de>
Diffstat (limited to 'arch/arm/cpu/armv7')
| -rw-r--r-- | arch/arm/cpu/armv7/mx6/soc.c | 29 |
1 files changed, 23 insertions, 6 deletions
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 60044bb..2ac74b5 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -40,18 +40,35 @@ u32 get_cpu_rev(void) #ifdef CONFIG_ARCH_CPU_INIT void init_aips(void) { - u32 reg = AIPS1_BASE_ADDR; + struct aipstz_regs *aips1, *aips2; + + aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR; + aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR; /* * Set all MPROTx to be non-bufferable, trusted for R/W, * not forced to user-mode. */ - writel(0x77777777, reg + 0x00); - writel(0x77777777, reg + 0x04); + writel(0x77777777, &aips1->mprot0); + writel(0x77777777, &aips1->mprot1); + writel(0x77777777, &aips2->mprot0); + writel(0x77777777, &aips2->mprot1); - reg = AIPS2_BASE_ADDR; - writel(0x77777777, reg + 0x00); - writel(0x77777777, reg + 0x04); + /* + * Set all OPACRx to be non-bufferable, not require + * supervisor privilege level for access,allow for + * write access and untrusted master access. + */ + writel(0x00000000, &aips1->opacr0); + writel(0x00000000, &aips1->opacr1); + writel(0x00000000, &aips1->opacr2); + writel(0x00000000, &aips1->opacr3); + writel(0x00000000, &aips1->opacr4); + writel(0x00000000, &aips2->opacr0); + writel(0x00000000, &aips2->opacr1); + writel(0x00000000, &aips2->opacr2); + writel(0x00000000, &aips2->opacr3); + writel(0x00000000, &aips2->opacr4); } int arch_cpu_init(void) |