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| author | Akshay Saraswat <akshay.s@samsung.com> | 2015-02-20 13:27:16 +0530 |
|---|---|---|
| committer | Minkyu Kang <mk7.kang@samsung.com> | 2015-02-28 18:03:46 +0900 |
| commit | f0f76b0a4c7181b2cbde39ec04eac8973cd4ad1f (patch) | |
| tree | 18e20093e11380866cbabd08762b16d3c9ce1ad7 /arch/arm/cpu/armv7 | |
| parent | 67a0652c47ec568ea274f5ff0303c9bba8ceddbf (diff) | |
| download | u-boot-imx-f0f76b0a4c7181b2cbde39ec04eac8973cd4ad1f.zip u-boot-imx-f0f76b0a4c7181b2cbde39ec04eac8973cd4ad1f.tar.gz u-boot-imx-f0f76b0a4c7181b2cbde39ec04eac8973cd4ad1f.tar.bz2 | |
Exynos542x: cache: Disable clean/evict push to external
L2 Auxiliary Control Register provides configuration
and control options for the L2 memory system. Bit 3
of L2ACTLR stands for clean/evict push to external.
Setting bit 3 disables clean/evict which is what
this patch intends to do.
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Diffstat (limited to 'arch/arm/cpu/armv7')
| -rw-r--r-- | arch/arm/cpu/armv7/exynos/soc.c | 18 |
1 files changed, 17 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv7/exynos/soc.c b/arch/arm/cpu/armv7/exynos/soc.c index 8c7d7d8..427f54c 100644 --- a/arch/arm/cpu/armv7/exynos/soc.c +++ b/arch/arm/cpu/armv7/exynos/soc.c @@ -13,7 +13,9 @@ enum l2_cache_params { CACHE_TAG_RAM_SETUP = (1 << 9), CACHE_DATA_RAM_SETUP = (1 << 5), CACHE_TAG_RAM_LATENCY = (2 << 6), - CACHE_DATA_RAM_LATENCY = (2 << 0) + CACHE_DATA_RAM_LATENCY = (2 << 0), + CACHE_ENABLE_CLEAN_EVICT = (0 << 3), + CACHE_DISABLE_CLEAN_EVICT = (1 << 3) }; void reset_cpu(ulong addr) @@ -37,14 +39,28 @@ static void exynos5_set_l2cache_params(void) { unsigned int val = 0; + /* Read L2CTLR value */ asm volatile("mrc p15, 1, %0, c9, c0, 2\n" : "=r"(val)); + /* Set cache setup and latency cycles */ val |= CACHE_TAG_RAM_SETUP | CACHE_DATA_RAM_SETUP | CACHE_TAG_RAM_LATENCY | CACHE_DATA_RAM_LATENCY; + /* Write new vlaue to L2CTLR */ asm volatile("mcr p15, 1, %0, c9, c0, 2\n" : : "r"(val)); + + if (proid_is_exynos5420() || proid_is_exynos5800()) { + /* Read L2ACTLR value */ + asm volatile("mrc p15, 1, %0, c15, c0, 0" : "=r" (val)); + + /* Disable clean/evict push to external */ + val |= CACHE_DISABLE_CLEAN_EVICT; + + /* Write new vlaue to L2ACTLR */ + asm volatile("mcr p15, 1, %0, c15, c0, 0" : : "r" (val)); + } } /* |