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| author | Chen-Yu Tsai <wens@csie.org> | 2016-01-06 15:13:07 +0800 |
|---|---|---|
| committer | Hans de Goede <hdegoede@redhat.com> | 2016-01-26 16:20:05 +0100 |
| commit | ed80584f3087f8d4da996cddd9807fc90f3de06c (patch) | |
| tree | 774b96da536519157b0280342229fbdb4478a85d /arch/arm/cpu/armv7 | |
| parent | 5823664fb84612ef511136b66059710cccd71bed (diff) | |
| download | u-boot-imx-ed80584f3087f8d4da996cddd9807fc90f3de06c.zip u-boot-imx-ed80584f3087f8d4da996cddd9807fc90f3de06c.tar.gz u-boot-imx-ed80584f3087f8d4da996cddd9807fc90f3de06c.tar.bz2 | |
sunxi: Support H3 CCU security switches
H3's CCU includes some switches which disable non-secure access to some
of the more critical clock controls, such as MBUS, PLLs, and main
platform busses.
Configure them to enable non-secure access.
For now the only SoC that has this feature is the H3. For other
platforms just use a default (weak) empty function so things do
not break.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Diffstat (limited to 'arch/arm/cpu/armv7')
| -rw-r--r-- | arch/arm/cpu/armv7/sunxi/clock.c | 5 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/sunxi/clock_sun6i.c | 13 |
2 files changed, 18 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/sunxi/clock.c b/arch/arm/cpu/armv7/sunxi/clock.c index 47fb70f..5cc5d25 100644 --- a/arch/arm/cpu/armv7/sunxi/clock.c +++ b/arch/arm/cpu/armv7/sunxi/clock.c @@ -14,12 +14,17 @@ #include <asm/arch/gpio.h> #include <asm/arch/sys_proto.h> +__weak void clock_init_sec(void) +{ +} + int clock_init(void) { #ifdef CONFIG_SPL_BUILD clock_init_safe(); #endif clock_init_uart(); + clock_init_sec(); return 0; } diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c index 1da5455..700b605 100644 --- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c +++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c @@ -45,6 +45,19 @@ void clock_init_safe(void) } #endif +void clock_init_sec(void) +{ +#ifdef CONFIG_MACH_SUN8I_H3 + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + setbits_le32(&ccm->ccu_sec_switch, + CCM_SEC_SWITCH_MBUS_NONSEC | + CCM_SEC_SWITCH_BUS_NONSEC | + CCM_SEC_SWITCH_PLL_NONSEC); +#endif +} + void clock_init_uart(void) { #if CONFIG_CONS_INDEX < 5 |