i.MX6: Add ANATOP regulator init

Init the core regulator voltage to 1.2V. This is required for the correct
functioning of the GPU and when the ARM LDO is set to 1.225V. This is a
workaround to fix some memory clock jitter.

Note: This should be but can't be done in the DCD. The bootloader
      prevents access to the ANATOP registers.

Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com>
CC: Jason Chen <b02280@freescale.com>
CC: Jason Liu <r64343@freescale.com>
CC: Ranjani Vaidyanathan <ra5478@freescale.com>
CC: Stefano Babic <sbabic@denx.de>
CC: Fabio Estevam <festevam@gmail.com>

1 files changed, 30 insertions, 0 deletions

diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index 543b2cc..90f2088 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -77,10 +77,40 @@ void init_aips(void)
 	writel(0x00000000, &aips2->opacr4);
 }
 
+/*
+ * Set the VDDSOC
+ *
+ * Mask out the REG_CORE[22:18] bits (REG2_TRIG) and set
+ * them to the specified millivolt level.
+ * Possible values are from 0.725V to 1.450V in steps of
+ * 0.025V (25mV).
+ */
+void set_vddsoc(u32 mv)
+{
+	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
+	u32 val, reg = readl(&anatop->reg_core);
+
+	if (mv < 725)
+		val = 0x00;	/* Power gated off */
+	else if (mv > 1450)
+		val = 0x1F;	/* Power FET switched full on. No regulation */
+	else
+		val = (mv - 700) / 25;
+
+	/*
+	 * Mask out the REG_CORE[22:18] bits (REG2_TRIG)
+	 * and set them to the calculated value (0.7V + val * 0.25V)
+	 */
+	reg = (reg & ~(0x1F << 18)) | (val << 18);
+	writel(reg, &anatop->reg_core);
+}
+
 int arch_cpu_init(void)
 {
 	init_aips();
 
+	set_vddsoc(1200);	/* Set VDDSOC to 1.2V */
+
 	return 0;
 }
 #endif