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authorRob Herring <rob.herring@calxeda.com>2013-06-12 22:24:49 -0500
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2013-07-25 08:15:33 +0200
commit714d1f5da53101ec44ab9c3d10564462b102bd8f (patch)
treea4be03f06301058de1f645e762d97e92a70c2aa2 /arch/arm/cpu/armv7
parentec0e413f934fd70968b4ca0daa530cbe8f5cdb4f (diff)
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ARM: highbank: set timer prescaler to 256
The 150MHz clock rate gives u-boot time functions problems and there's no benefit to a fast clock, so lower the rate. Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Diffstat (limited to 'arch/arm/cpu/armv7')
-rw-r--r--arch/arm/cpu/armv7/highbank/timer.c6
1 files changed, 4 insertions, 2 deletions
diff --git a/arch/arm/cpu/armv7/highbank/timer.c b/arch/arm/cpu/armv7/highbank/timer.c
index da33d3c..d93de1e 100644
--- a/arch/arm/cpu/armv7/highbank/timer.c
+++ b/arch/arm/cpu/armv7/highbank/timer.c
@@ -26,7 +26,7 @@
#undef SYSTIMER_BASE
#define SYSTIMER_BASE 0xFFF34000 /* Timer 0 and 1 base */
-#define SYSTIMER_RATE 150000000
+#define SYSTIMER_RATE (150000000 / 256)
static ulong timestamp;
static ulong lastinc;
@@ -40,9 +40,11 @@ int timer_init(void)
/*
* Setup timer0
*/
+ writel(0, &systimer_base->timer0control);
writel(SYSTIMER_RELOAD, &systimer_base->timer0load);
writel(SYSTIMER_RELOAD, &systimer_base->timer0value);
- writel(SYSTIMER_EN | SYSTIMER_32BIT, &systimer_base->timer0control);
+ writel(SYSTIMER_EN | SYSTIMER_32BIT | SYSTIMER_PRESC_256,
+ &systimer_base->timer0control);
reset_timer_masked();