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| author | Vikas Manocha <vikas.manocha@st.com> | 2014-11-18 10:42:23 -0800 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2014-12-09 15:16:19 -0500 |
| commit | 2ce4eaf4c89e371aeb69392b68dbb2f705c28144 (patch) | |
| tree | 56c27ac25726f80f1bf7844222f8fadea3cdec8a /arch/arm/cpu/armv7 | |
| parent | 9fa32b12370236a39090d4e42b013910d123db61 (diff) | |
| download | u-boot-imx-2ce4eaf4c89e371aeb69392b68dbb2f705c28144.zip u-boot-imx-2ce4eaf4c89e371aeb69392b68dbb2f705c28144.tar.gz u-boot-imx-2ce4eaf4c89e371aeb69392b68dbb2f705c28144.tar.bz2 | |
stv0991: enable ethernet support
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Diffstat (limited to 'arch/arm/cpu/armv7')
| -rw-r--r-- | arch/arm/cpu/armv7/stv0991/clock.c | 14 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/stv0991/pinmux.c | 14 |
2 files changed, 28 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/stv0991/clock.c b/arch/arm/cpu/armv7/stv0991/clock.c index aca6aba..70b8a8d 100644 --- a/arch/arm/cpu/armv7/stv0991/clock.c +++ b/arch/arm/cpu/armv7/stv0991/clock.c @@ -13,6 +13,13 @@ static struct stv0991_cgu_regs *const stv0991_cgu_regs = \ (struct stv0991_cgu_regs *) (CGU_BASE_ADDR); +void enable_pll1(void) +{ + /* pll1 already configured for 1000Mhz, just need to enable it */ + writel(readl(&stv0991_cgu_regs->pll1_ctrl) & ~(0x01), + &stv0991_cgu_regs->pll1_ctrl); +} + void clock_setup(int peripheral) { switch (peripheral) { @@ -20,6 +27,13 @@ void clock_setup(int peripheral) writel(UART_CLK_CFG, &stv0991_cgu_regs->uart_freq); break; case ETH_CLOCK_CFG: + enable_pll1(); + writel(ETH_CLK_CFG, &stv0991_cgu_regs->eth_freq); + + /* Clock selection for ethernet tx_clk & rx_clk*/ + writel((readl(&stv0991_cgu_regs->eth_ctrl) & ETH_CLK_MASK) + | ETH_CLK_CTRL, &stv0991_cgu_regs->eth_ctrl); + break; default: break; diff --git a/arch/arm/cpu/armv7/stv0991/pinmux.c b/arch/arm/cpu/armv7/stv0991/pinmux.c index 6d4414a..1d086a2 100644 --- a/arch/arm/cpu/armv7/stv0991/pinmux.c +++ b/arch/arm/cpu/armv7/stv0991/pinmux.c @@ -41,6 +41,20 @@ int stv0991_pinmux_config(int peripheral) CFG_GPIOB_16_UART_TX, &stv0991_creg->mux7); break; + case ETH_GPIOB_10_31_C_0_4: + writel(readl(&stv0991_creg->mux6) & 0x000000FF, + &stv0991_creg->mux6); + writel(0x00000000, &stv0991_creg->mux7); + writel(0x00000000, &stv0991_creg->mux8); + writel(readl(&stv0991_creg->mux9) & 0xFFF00000, + &stv0991_creg->mux9); + /* Ethernet Voltage configuration to 1.8V*/ + writel((readl(&stv0991_creg->vdd_pad1) & VDD_ETH_PS_MASK) | + ETH_VDD_CFG, &stv0991_creg->vdd_pad1); + writel((readl(&stv0991_creg->vdd_pad1) & VDD_ETH_PS_MASK) | + ETH_M_VDD_CFG, &stv0991_creg->vdd_pad1); + + break; default: break; } |