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| author | Akshay Saraswat <akshay.s@samsung.com> | 2014-11-13 22:38:20 +0530 |
|---|---|---|
| committer | Minkyu Kang <mk7.kang@samsung.com> | 2014-11-17 19:03:38 +0900 |
| commit | 0e03e824652745d652c6b557307fa784ec1669aa (patch) | |
| tree | 29731928d60cdb75ee5655caa48f3467f20b6487 /arch/arm/cpu/armv7 | |
| parent | 43581c833876314b3cf556805465a3ab8d86d244 (diff) | |
| download | u-boot-imx-0e03e824652745d652c6b557307fa784ec1669aa.zip u-boot-imx-0e03e824652745d652c6b557307fa784ec1669aa.tar.gz u-boot-imx-0e03e824652745d652c6b557307fa784ec1669aa.tar.bz2 | |
Exynos5: ddr3: Choose between single or double channel config
Add a 4G configuration and choose it based on the number of banks
declared in config file. A board with 4 SDRAM banks declared (as
per CONFIG_NR_DRAM_BANKS) will end up with the 2G confiuration.
Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Diffstat (limited to 'arch/arm/cpu/armv7')
| -rw-r--r-- | arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c index 4d73b45..7c0b12a 100644 --- a/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c +++ b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c @@ -464,6 +464,16 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset) + DMC_OFFSET); pmu = (struct exynos5_power *)EXYNOS5420_POWER_BASE; + if (CONFIG_NR_DRAM_BANKS > 4) { + /* Need both controllers. */ + mem->memcontrol |= DMC_MEMCONTROL_NUM_CHIP_2; + mem->chips_per_channel = 2; + mem->chips_to_configure = 2; + } else { + /* 2GB requires a single controller */ + mem->memcontrol |= DMC_MEMCONTROL_NUM_CHIP_1; + } + /* Enable PAUSE for DREX */ setbits_le32(&clk->pause, ENABLE_BIT); |