diff options
author | Ye.Li <B37916@freescale.com> | 2014-06-10 15:21:42 +0800 |
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committer | Ye.Li <B37916@freescale.com> | 2014-06-17 11:13:52 +0800 |
commit | 070c01291e25f4f16cd0df971ddb6c67a0a57152 (patch) | |
tree | b25884ba453c67ee8ac640ac2a3e239b90198839 /arch/arm/cpu/armv7 | |
parent | e06f5f5271ec35d8151bd4eeee785df8c80db011 (diff) | |
download | u-boot-imx-070c01291e25f4f16cd0df971ddb6c67a0a57152.zip u-boot-imx-070c01291e25f4f16cd0df971ddb6c67a0a57152.tar.gz u-boot-imx-070c01291e25f4f16cd0df971ddb6c67a0a57152.tar.bz2 |
ENGR00315894-48 iMX6SX: Add iMX6SX SoC support
Adding clks, pinmux, memory map, etc for iMX6SoloX.
Signed-off-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Jason Liu <r64343@freescale.com>
Signed-off-by: Frank Li <Frank.Li@freescale.com>
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
Diffstat (limited to 'arch/arm/cpu/armv7')
-rw-r--r-- | arch/arm/cpu/armv7/mx6/clock.c | 12 | ||||
-rw-r--r-- | arch/arm/cpu/armv7/mx6/soc.c | 37 |
2 files changed, 47 insertions, 2 deletions
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index 625518a..da8ba76 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -214,7 +214,7 @@ static u32 get_uart_clk(void) u32 reg, uart_podf; u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */ reg = __raw_readl(&imx_ccm->cscdr1); -#ifdef CONFIG_MX6SL +#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX)) if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL) freq = MXC_HCLK; #endif @@ -282,7 +282,7 @@ static u32 get_emi_slow_clk(void) return root_freq / (emi_slow_podf + 1); } -#ifdef CONFIG_MX6SL +#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX)) static u32 get_mmdc_ch0_clk(void) { u32 cbcmr = __raw_readl(&imx_ccm->cbcmr); @@ -437,6 +437,7 @@ static int enable_enet_pll(uint32_t en) return 0; } +#ifndef CONFIG_MX6SX static void ungate_sata_clock(void) { struct mxc_ccm_reg *const imx_ccm = @@ -445,6 +446,7 @@ static void ungate_sata_clock(void) /* Enable SATA clock. */ setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK); } +#endif static void ungate_pcie_clock(void) { @@ -455,11 +457,13 @@ static void ungate_pcie_clock(void) setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK); } +#ifndef CONFIG_MX6SX int enable_sata_clock(void) { ungate_sata_clock(); return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA); } +#endif int enable_pcie_clock(void) { @@ -491,7 +495,9 @@ int enable_pcie_clock(void) clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL); /* Party time! Ungate the clock to the PCIe. */ +#ifndef CONFIG_MX6SX ungate_sata_clock(); +#endif ungate_pcie_clock(); return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA | @@ -611,6 +617,7 @@ int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 0; } +#ifndef CONFIG_MX6SX void enable_ipu_clock(void) { struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; @@ -619,6 +626,7 @@ void enable_ipu_clock(void) reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK; writel(reg, &mxc_ccm->CCGR3); } +#endif /***************************************************/ U_BOOT_CMD( diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index adc123f..88cb2bb 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -101,9 +101,15 @@ u32 __weak get_board_rev(void) void init_aips(void) { struct aipstz_regs *aips1, *aips2; +#ifdef CONFIG_MX6SX + struct aipstz_regs *aips3; +#endif aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR; aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR; +#ifdef CONFIG_MX6SX + aips3 = (struct aipstz_regs *)AIPS3_CONFIG_BASE_ADDR; +#endif /* * Set all MPROTx to be non-bufferable, trusted for R/W, @@ -129,6 +135,26 @@ void init_aips(void) writel(0x00000000, &aips2->opacr2); writel(0x00000000, &aips2->opacr3); writel(0x00000000, &aips2->opacr4); + +#ifdef CONFIG_MX6SX + /* + * Set all MPROTx to be non-bufferable, trusted for R/W, + * not forced to user-mode. + */ + writel(0x77777777, &aips3->mprot0); + writel(0x77777777, &aips3->mprot1); + + /* + * Set all OPACRx to be non-bufferable, not require + * supervisor privilege level for access,allow for + * write access and untrusted master access. + */ + writel(0x00000000, &aips3->opacr0); + writel(0x00000000, &aips3->opacr1); + writel(0x00000000, &aips3->opacr2); + writel(0x00000000, &aips3->opacr3); + writel(0x00000000, &aips3->opacr4); +#endif } static void clear_ldo_ramp(void) @@ -375,9 +401,15 @@ static void imx_set_pcie_phy_power_down(void) { u32 val; +#ifndef CONFIG_MX6SX val = readl(IOMUXC_BASE_ADDR + 0x4); val |= 0x1 << 18; writel(val, IOMUXC_BASE_ADDR + 0x4); +#else + val = readl(IOMUXC_GPR_BASE_ADDR + 0x30); + val |= 0x1 << 30; + writel(val, IOMUXC_GPR_BASE_ADDR + 0x30); +#endif } int arch_cpu_init(void) @@ -543,9 +575,14 @@ void s_init(void) { struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; int is_6q = is_cpu_type(MXC_CPU_MX6Q); + int is_6sx = is_cpu_type(MXC_CPU_MX6SX); u32 mask480; u32 mask528; + /* Don't reset PFD for MX6SX */ + if (is_6sx) + return; + /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs * to make sure PFD is working right, otherwise, PFDs may * not output clock after reset, MX6DL and MX6SL have added 396M pfd |