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authorFabio Estevam <fabio.estevam@freescale.com>2012-03-13 07:26:48 +0000
committerStefano Babic <sbabic@denx.de>2012-03-27 09:41:16 +0200
commitcece262209aaacf6f842c8d15832f882eb2467d8 (patch)
tree120ab774df6120121c3124f4e029bb4b7feff53f /arch/arm/cpu/armv7
parentc338f0b5c60d3b133139539fdfc39d2f2cb29b06 (diff)
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mx6: Fix reset cause for Power On Reset case
After booting mx6qsabrelite from POR the following is reported: CPU: Freescale i.MX61 family rev1.0 at 792 MHz Reset cause: unknown reset This is because both the POR and WDOG bits are set after reset. Fix this by also checking both bits in the POR case. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Diffstat (limited to 'arch/arm/cpu/armv7')
-rw-r--r--arch/arm/cpu/armv7/imx-common/cpu.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/imx-common/cpu.c b/arch/arm/cpu/armv7/imx-common/cpu.c
index 1e30ae5..6d7486b 100644
--- a/arch/arm/cpu/armv7/imx-common/cpu.c
+++ b/arch/arm/cpu/armv7/imx-common/cpu.c
@@ -44,6 +44,7 @@ static char *get_reset_cause(void)
switch (cause) {
case 0x00001:
+ case 0x00011:
return "POR";
case 0x00004:
return "CSU";