From cece262209aaacf6f842c8d15832f882eb2467d8 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 13 Mar 2012 07:26:48 +0000 Subject: mx6: Fix reset cause for Power On Reset case After booting mx6qsabrelite from POR the following is reported: CPU: Freescale i.MX61 family rev1.0 at 792 MHz Reset cause: unknown reset This is because both the POR and WDOG bits are set after reset. Fix this by also checking both bits in the POR case. Signed-off-by: Fabio Estevam --- arch/arm/cpu/armv7/imx-common/cpu.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/cpu/armv7') diff --git a/arch/arm/cpu/armv7/imx-common/cpu.c b/arch/arm/cpu/armv7/imx-common/cpu.c index 1e30ae5..6d7486b 100644 --- a/arch/arm/cpu/armv7/imx-common/cpu.c +++ b/arch/arm/cpu/armv7/imx-common/cpu.c @@ -44,6 +44,7 @@ static char *get_reset_cause(void) switch (cause) { case 0x00001: + case 0x00011: return "POR"; case 0x00004: return "CSU"; -- cgit v1.1