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author | Masahiro Yamada <yamada.m@jp.panasonic.com> | 2014-11-06 20:16:42 +0900 |
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committer | Masahiro Yamada <yamada.m@jp.panasonic.com> | 2014-11-12 00:16:08 +0900 |
commit | a69e037e46f028f5baafc4b3740e21bcadd5a33d (patch) | |
tree | 55f8b9095a9634583ce57ecc2b45ea73db319dcd /arch/arm/cpu/armv7/uniphier/ph1-ld4 | |
parent | b603c6812919ccb51680735faf1f8c589e82575c (diff) | |
download | u-boot-imx-a69e037e46f028f5baafc4b3740e21bcadd5a33d.zip u-boot-imx-a69e037e46f028f5baafc4b3740e21bcadd5a33d.tar.gz u-boot-imx-a69e037e46f028f5baafc4b3740e21bcadd5a33d.tar.bz2 |
ARM: UniPhier: move DDR related configuration to Kconfig
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Diffstat (limited to 'arch/arm/cpu/armv7/uniphier/ph1-ld4')
-rw-r--r-- | arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile | 3 | ||||
-rw-r--r-- | arch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.c | 4 |
2 files changed, 1 insertions, 6 deletions
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile b/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile index 781b511..5722ee2 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile +++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile @@ -7,5 +7,4 @@ obj-y += platdevice.o obj-y += boot-mode.o obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o bcu_init.o \ sbc_init.o sg_init.o pll_init.o clkrst_init.o pinctrl.o -obj-$(CONFIG_SPL_BUILD) += pll_spectrum.o \ - umc_init.o +obj-$(CONFIG_DRAM_INIT) += pll_spectrum.o umc_init.o diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.c index 1344ac1..ebcbaab 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.c +++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.c @@ -149,10 +149,6 @@ int umc_init(void) CONFIG_SDRAM1_SIZE / 0x08000000); } -#if CONFIG_DDR_FREQ != 1333 && CONFIG_DDR_FREQ != 1600 -#error Unsupported DDR Frequency. -#endif - #if (CONFIG_SDRAM0_SIZE == 0x08000000 || CONFIG_SDRAM0_SIZE == 0x10000000) && \ (CONFIG_SDRAM1_SIZE == 0x08000000 || CONFIG_SDRAM1_SIZE == 0x10000000) && \ CONFIG_DDR_NUM_CH0 == 1 && CONFIG_DDR_NUM_CH1 == 1 |