diff options
author | Simon Glass <sjg@chromium.org> | 2012-04-19 08:04:39 +0000 |
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committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2012-07-07 14:07:19 +0200 |
commit | 27c4a3318f716cce0a23248317534bda7792230b (patch) | |
tree | 74daff034784a48106de6ca2a4bd814066279389 /arch/arm/cpu/armv7/tegra2/clock.c | |
parent | 00a55add04222539846dd884217bcf40c504da92 (diff) | |
download | u-boot-imx-27c4a3318f716cce0a23248317534bda7792230b.zip u-boot-imx-27c4a3318f716cce0a23248317534bda7792230b.tar.gz u-boot-imx-27c4a3318f716cce0a23248317534bda7792230b.tar.bz2 |
tegra: Correct PLL access in ap20.c and clock.c
Correct this warning seen by Albert:
ap20.c:44:18: warning: array subscript is above array bounds
There is a subtle bug here which currently causes no errors, but might
in future if people use PCI or the 32KHz clock. So take the opportunity
to correct the logic now.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'arch/arm/cpu/armv7/tegra2/clock.c')
-rw-r--r-- | arch/arm/cpu/armv7/tegra2/clock.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/cpu/armv7/tegra2/clock.c b/arch/arm/cpu/armv7/tegra2/clock.c index ccad351..602589c 100644 --- a/arch/arm/cpu/armv7/tegra2/clock.c +++ b/arch/arm/cpu/armv7/tegra2/clock.c @@ -426,7 +426,7 @@ static struct clk_pll *get_pll(enum clock_id clkid) struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; - assert(clock_id_isvalid(clkid)); + assert(clock_id_is_pll(clkid)); return &clkrst->crc_pll[clkid]; } @@ -439,7 +439,7 @@ int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn, assert(clkid != CLOCK_ID_USB); /* Safety check, adds to code size but is small */ - if (!clock_id_isvalid(clkid) || clkid == CLOCK_ID_USB) + if (!clock_id_is_pll(clkid) || clkid == CLOCK_ID_USB) return -1; data = readl(&pll->pll_base); *divm = (data & PLL_DIVM_MASK) >> PLL_DIVM_SHIFT; |