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authorAllen Martin <amartin@nvidia.com>2012-08-31 08:30:12 +0000
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2012-09-01 14:58:22 +0200
commit12b7b70cb01e284a7ca430d90f3e93bcc2daefec (patch)
tree339e969b69c35cce8e84d5a8bda5be39e7e356bf /arch/arm/cpu/armv7/start.S
parenta49716aa7cda96f5e8cd15e57587da7a99f9e330 (diff)
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tegra20: enable SPL for tegra20 boards
Add SPL options to tegra20 config files and enable SPL build for tegra20 boards. Also remove redundant code from u-boot that is not contained in SPL. Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'arch/arm/cpu/armv7/start.S')
-rw-r--r--arch/arm/cpu/armv7/start.S2
1 files changed, 0 insertions, 2 deletions
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 38cce93..b06bafd 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -133,7 +133,6 @@ reset:
orr r0, r0, #0xd3
msr cpsr,r0
-#if !defined(CONFIG_TEGRA20)
/*
* Setup vector:
* (OMAP4 spl TEXT_BASE is not 32 byte aligned.
@@ -149,7 +148,6 @@ reset:
ldr r0, =_start
mcr p15, 0, r0, c12, c0, 0 @Set VBAR
#endif
-#endif /* !Tegra20 */
/* the mask ROM code should have PLL and others stable */
#ifndef CONFIG_SKIP_LOWLEVEL_INIT