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authorSRICHARAN R <r.sricharan@ti.com>2013-02-12 01:33:43 +0000
committerTom Rini <trini@ti.com>2013-03-11 11:06:10 -0400
commit47abc3df701d8bc26f311350aa523fc1d0f8ad4e (patch)
tree057c11204cfdc270720f49af35258b2708caa6e4 /arch/arm/cpu/armv7/omap4
parentafc2f9dcf1a4a478e51a84b1a162bca19c7b7715 (diff)
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ARM: OMAP4/5: clocks: Add the required OPP settings as per the latest addendum
Change OPP settings as per the latest 0.5 version of addendum for OMAP5430 ES2.0. omap4/hw_data.c is touched here to add dummy dividers. While here correcting OPP_NOM mpu, core frequency for OMAP4430 ES2.x Note that OMAP5430 ES1.0 support is still kept alive and would be removed in a cleanup later. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: R Sricharan <r.sricharan@ti.com> Cc: Tom Rini <trini@ti.com> Cc: Nishanth Menon <nm@ti.com>
Diffstat (limited to 'arch/arm/cpu/armv7/omap4')
-rw-r--r--arch/arm/cpu/armv7/omap4/hw_data.c164
1 files changed, 88 insertions, 76 deletions
diff --git a/arch/arm/cpu/armv7/omap4/hw_data.c b/arch/arm/cpu/armv7/omap4/hw_data.c
index 892d016..8d31d6d 100644
--- a/arch/arm/cpu/armv7/omap4/hw_data.c
+++ b/arch/arm/cpu/armv7/omap4/hw_data.c
@@ -49,115 +49,127 @@ struct omap_sys_ctrl_regs const **ctrl =
* Please use this tool for creating the table for any new frequency.
*/
-/* dpll locked at 1400 MHz MPU clk at 700 MHz(OPP100) - DCC OFF */
+/*
+ * dpll locked at 1400 MHz MPU clk at 700 MHz(OPP100) - DCC OFF
+ * OMAP4460 OPP_NOM frequency
+ */
static const struct dpll_params mpu_dpll_params_1400mhz[NUM_SYS_CLKS] = {
- {175, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
- {700, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {125, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
- {401, 10, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {350, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
- {700, 26, 1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {638, 34, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
+ {175, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {700, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {401, 10, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {350, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {700, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {638, 34, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
-/* dpll locked at 1584 MHz - MPU clk at 792 MHz(OPP Turbo 4430) */
+/*
+ * dpll locked at 1600 MHz - MPU clk at 800 MHz(OPP Turbo 4430)
+ * OMAP4430 OPP_TURBO frequency
+ */
static const struct dpll_params mpu_dpll_params_1600mhz[NUM_SYS_CLKS] = {
- {200, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
- {800, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {619, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
- {125, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {400, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
- {800, 26, 1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {125, 5, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
+ {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {800, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {619, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {800, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {125, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
-/* dpll locked at 1200 MHz - MPU clk at 600 MHz */
+/*
+ * dpll locked at 1200 MHz - MPU clk at 600 MHz
+ * OMAP4430 OPP_NOM frequency
+ */
static const struct dpll_params mpu_dpll_params_1200mhz[NUM_SYS_CLKS] = {
- {50, 0, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
- {600, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {250, 6, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
- {125, 3, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {300, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
- {200, 8, 1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {125, 7, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
+ {50, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {600, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {250, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {125, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {300, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {200, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {125, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
+/* OMAP4460 OPP_NOM frequency */
static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = {
- {200, 2, 1, 5, 8, 4, 6, 5, -1, -1}, /* 12 MHz */
- {800, 12, 1, 5, 8, 4, 6, 5, -1, -1}, /* 13 MHz */
- {619, 12, 1, 5, 8, 4, 6, 5, -1, -1}, /* 16.8 MHz */
- {125, 2, 1, 5, 8, 4, 6, 5, -1, -1}, /* 19.2 MHz */
- {400, 12, 1, 5, 8, 4, 6, 5, -1, -1}, /* 26 MHz */
- {800, 26, 1, 5, 8, 4, 6, 5, -1, -1}, /* 27 MHz */
- {125, 5, 1, 5, 8, 4, 6, 5, -1, -1} /* 38.4 MHz */
+ {200, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */
+ {800, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */
+ {619, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */
+ {125, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */
+ {400, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */
+ {800, 26, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */
+ {125, 5, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */
};
+/* OMAP4430 ES1 OPP_NOM frequency */
static const struct dpll_params core_dpll_params_es1_1524mhz[NUM_SYS_CLKS] = {
- {127, 1, 1, 5, 8, 4, 6, 5, -1, -1}, /* 12 MHz */
- {762, 12, 1, 5, 8, 4, 6, 5, -1, -1}, /* 13 MHz */
- {635, 13, 1, 5, 8, 4, 6, 5, -1, -1}, /* 16.8 MHz */
- {635, 15, 1, 5, 8, 4, 6, 5, -1, -1}, /* 19.2 MHz */
- {381, 12, 1, 5, 8, 4, 6, 5, -1, -1}, /* 26 MHz */
- {254, 8, 1, 5, 8, 4, 6, 5, -1, -1}, /* 27 MHz */
- {496, 24, 1, 5, 8, 4, 6, 5, -1, -1} /* 38.4 MHz */
+ {127, 1, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */
+ {762, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */
+ {635, 13, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */
+ {635, 15, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */
+ {381, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */
+ {254, 8, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */
+ {496, 24, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */
};
+/* OMAP4430 ES2.X OPP_NOM frequency */
static const struct dpll_params
core_dpll_params_es2_1600mhz_ddr200mhz[NUM_SYS_CLKS] = {
- {200, 2, 2, 5, 8, 4, 6, 5, -1, -1}, /* 12 MHz */
- {800, 12, 2, 5, 8, 4, 6, 5, -1, -1}, /* 13 MHz */
- {619, 12, 2, 5, 8, 4, 6, 5, -1, -1}, /* 16.8 MHz */
- {125, 2, 2, 5, 8, 4, 6, 5, -1, -1}, /* 19.2 MHz */
- {400, 12, 2, 5, 8, 4, 6, 5, -1, -1}, /* 26 MHz */
- {800, 26, 2, 5, 8, 4, 6, 5, -1, -1}, /* 27 MHz */
- {125, 5, 2, 5, 8, 4, 6, 5, -1, -1} /* 38.4 MHz */
+ {200, 2, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */
+ {800, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */
+ {619, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */
+ {125, 2, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */
+ {400, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */
+ {800, 26, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */
+ {125, 5, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */
};
static const struct dpll_params per_dpll_params_1536mhz[NUM_SYS_CLKS] = {
- {64, 0, 8, 6, 12, 9, 4, 5, -1, -1}, /* 12 MHz */
- {768, 12, 8, 6, 12, 9, 4, 5, -1, -1}, /* 13 MHz */
- {320, 6, 8, 6, 12, 9, 4, 5, -1, -1}, /* 16.8 MHz */
- {40, 0, 8, 6, 12, 9, 4, 5, -1, -1}, /* 19.2 MHz */
- {384, 12, 8, 6, 12, 9, 4, 5, -1, -1}, /* 26 MHz */
- {256, 8, 8, 6, 12, 9, 4, 5, -1, -1}, /* 27 MHz */
- {20, 0, 8, 6, 12, 9, 4, 5, -1, -1} /* 38.4 MHz */
+ {64, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 12 MHz */
+ {768, 12, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 13 MHz */
+ {320, 6, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 16.8 MHz */
+ {40, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 19.2 MHz */
+ {384, 12, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 26 MHz */
+ {256, 8, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 27 MHz */
+ {20, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1} /* 38.4 MHz */
};
static const struct dpll_params iva_dpll_params_1862mhz[NUM_SYS_CLKS] = {
- {931, 11, -1, -1, 4, 7, -1, -1, -1, -1}, /* 12 MHz */
- {931, 12, -1, -1, 4, 7, -1, -1, -1, -1}, /* 13 MHz */
- {665, 11, -1, -1, 4, 7, -1, -1, -1, -1}, /* 16.8 MHz */
- {727, 14, -1, -1, 4, 7, -1, -1, -1, -1}, /* 19.2 MHz */
- {931, 25, -1, -1, 4, 7, -1, -1, -1, -1}, /* 26 MHz */
- {931, 26, -1, -1, 4, 7, -1, -1, -1, -1}, /* 27 MHz */
- {291, 11, -1, -1, 4, 7, -1, -1, -1, -1} /* 38.4 MHz */
+ {931, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {931, 12, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {665, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {727, 14, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {931, 25, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {931, 26, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {291, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
/* ABE M & N values with sys_clk as source */
static const struct dpll_params
abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
- {49, 5, 1, 1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
- {68, 8, 1, 1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {35, 5, 1, 1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
- {46, 8, 1, 1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {34, 8, 1, 1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
- {29, 7, 1, 1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {64, 24, 1, 1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
+ {49, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {68, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {29, 7, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
/* ABE M & N values with 32K clock as source */
static const struct dpll_params abe_dpll_params_32k_196608khz = {
- 750, 0, 1, 1, -1, -1, -1, -1, -1, -1
+ 750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1
};
static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
- {80, 0, 2, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
- {960, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {400, 6, 2, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
- {50, 0, 2, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {480, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
- {320, 8, 2, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {25, 0, 2, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
+ {80, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {960, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {50, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {320, 8, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {25, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
struct dplls omap4430_dplls_es1 = {
@@ -174,8 +186,8 @@ struct dplls omap4430_dplls_es1 = {
};
struct dplls omap4430_dplls = {
- .mpu = mpu_dpll_params_1600mhz,
- .core = core_dpll_params_es2_1600mhz_ddr200mhz,
+ .mpu = mpu_dpll_params_1200mhz,
+ .core = core_dpll_params_1600mhz,
.per = per_dpll_params_1536mhz,
.iva = iva_dpll_params_1862mhz,
#ifdef CONFIG_SYS_OMAP_ABE_SYSCK