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| author | Ye Li <ye.li@nxp.com> | 2017-03-13 14:03:53 +0800 |
|---|---|---|
| committer | Ye Li <ye.li@nxp.com> | 2017-03-14 22:26:49 +0800 |
| commit | 7e6d3c66aa9204bda40275a3fe78ba0dcfc82638 (patch) | |
| tree | 3269b65430f5f611b32b697e272a78f5aa63cb1a /arch/arm/cpu/armv7/mx7/soc.c | |
| parent | 95fa940015031aa12d339fa86a115a3b4e423416 (diff) | |
| download | u-boot-imx-7e6d3c66aa9204bda40275a3fe78ba0dcfc82638.zip u-boot-imx-7e6d3c66aa9204bda40275a3fe78ba0dcfc82638.tar.gz u-boot-imx-7e6d3c66aa9204bda40275a3fe78ba0dcfc82638.tar.bz2 | |
MLK-14417 imx: Enable ACTLR.SMP bit for all i.MX cortex-a7 platforms
According to the Cortex-A7 TRM, for ACTLR.SMP bit "You must ensure this bit
is set to 1 before the caches and MMU are enabled, or any cache and TLB
maintenance operations are performed".
ROM sets this bit in normal boot flow, but when in serial download mode, it is not set.
Here we add it in u-boot as a common flow for all i.MX cortex-a7 platforms,
including mx7d, mx6ul/ull and mx7ulp.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 14990af03450f3e1898135c86fd8b93328007617)
Diffstat (limited to 'arch/arm/cpu/armv7/mx7/soc.c')
| -rw-r--r-- | arch/arm/cpu/armv7/mx7/soc.c | 8 |
1 files changed, 1 insertions, 7 deletions
diff --git a/arch/arm/cpu/armv7/mx7/soc.c b/arch/arm/cpu/armv7/mx7/soc.c index 580e127..ad8ca49 100644 --- a/arch/arm/cpu/armv7/mx7/soc.c +++ b/arch/arm/cpu/armv7/mx7/soc.c @@ -1,5 +1,6 @@ /* * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * Copyright (C) 2017 NXP * * SPDX-License-Identifier: GPL-2.0+ */ @@ -448,13 +449,6 @@ int mmc_get_env_dev(void) void s_init(void) { -#if !defined CONFIG_SPL_BUILD - /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */ - asm volatile( - "mrc p15, 0, r0, c1, c0, 1\n" - "orr r0, r0, #1 << 6\n" - "mcr p15, 0, r0, c1, c0, 1\n"); -#endif /* clock configuration. */ clock_init(); |