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| author | Tom Rini <trini@konsulko.com> | 2016-01-25 10:40:38 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2016-01-25 10:40:38 -0500 |
| commit | 2218c54bc13c8045903afc05d1364439a230da1f (patch) | |
| tree | 04c07b31c7953846b907fab4a4609a38e312b4ab /arch/arm/cpu/armv7/mx7/soc.c | |
| parent | cc4228f9d69f58495c2404adba9145bb36e613bf (diff) | |
| parent | ed3fb1fb22fb9e0e786c58c2d80cd030b89b9b7d (diff) | |
| download | u-boot-imx-2218c54bc13c8045903afc05d1364439a230da1f.zip u-boot-imx-2218c54bc13c8045903afc05d1364439a230da1f.tar.gz u-boot-imx-2218c54bc13c8045903afc05d1364439a230da1f.tar.bz2 | |
Merge branch 'master' of git://git.denx.de/u-boot-imx
Diffstat (limited to 'arch/arm/cpu/armv7/mx7/soc.c')
| -rw-r--r-- | arch/arm/cpu/armv7/mx7/soc.c | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/mx7/soc.c b/arch/arm/cpu/armv7/mx7/soc.c index c777922..1d8e470 100644 --- a/arch/arm/cpu/armv7/mx7/soc.c +++ b/arch/arm/cpu/armv7/mx7/soc.c @@ -130,6 +130,24 @@ static void init_csu(void) writel(CSU_INIT_SEC_LEVEL0, CSU_IPS_BASE_ADDR + i * 4); } +static void imx_enet_mdio_fixup(void) +{ + struct iomuxc_gpr_base_regs *gpr_regs = + (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; + + /* + * The management data input/output (MDIO) requires open-drain, + * i.MX7D TO1.0 ENET MDIO pin has no open drain, but TO1.1 supports + * this feature. So to TO1.1, need to enable open drain by setting + * bits GPR0[8:7]. + */ + + if (soc_rev() >= CHIP_REV_1_1) { + setbits_le32(&gpr_regs->gpr[0], + IOMUXC_GPR_GPR0_ENET_MDIO_OPEN_DRAIN_MASK); + } +} + int arch_cpu_init(void) { init_aips(); @@ -138,6 +156,8 @@ int arch_cpu_init(void) /* Disable PDE bit of WMCR register */ imx_set_wdog_powerdown(false); + imx_enet_mdio_fixup(); + #ifdef CONFIG_APBH_DMA /* Start APBH DMA */ mxs_dma_init(); |