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| author | Eric Nelson <eric.nelson@boundarydevices.com> | 2013-08-29 12:41:46 -0700 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2013-08-31 18:09:37 +0200 |
| commit | 8467faef7fce8c5faad7224b7737a58e16c52186 (patch) | |
| tree | 596ffbc6350f36c894beec57eb2fc46d4944c49b /arch/arm/cpu/armv7/mx6/soc.c | |
| parent | 67d54c39178aef2ea691c09dc115ed44ea92f46e (diff) | |
| download | u-boot-imx-8467faef7fce8c5faad7224b7737a58e16c52186.zip u-boot-imx-8467faef7fce8c5faad7224b7737a58e16c52186.tar.gz u-boot-imx-8467faef7fce8c5faad7224b7737a58e16c52186.tar.bz2 | |
i.MX6: Set and clear the gating bits for Phase Fractional Dividers
This addresses silicon errata ERR006282 as described in this
document:
https://community.freescale.com/docs/DOC-94581
Also implemented in Freescale's 2009.08-based release:
http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/
Commit id: b7c5badf94ffbe6cd0845efbb75e16e05e3af404
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Diffstat (limited to 'arch/arm/cpu/armv7/mx6/soc.c')
| -rw-r--r-- | arch/arm/cpu/armv7/mx6/soc.c | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 8150bff..a390296 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -213,6 +213,34 @@ const struct boot_mode soc_boot_modes[] = { void s_init(void) { + struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; + int is_6q = is_cpu_type(MXC_CPU_MX6Q); + u32 mask480; + u32 mask528; + + /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs + * to make sure PFD is working right, otherwise, PFDs may + * not output clock after reset, MX6DL and MX6SL have added 396M pfd + * workaround in ROM code, as bus clock need it + */ + + mask480 = ANATOP_PFD_CLKGATE_MASK(0) | + ANATOP_PFD_CLKGATE_MASK(1) | + ANATOP_PFD_CLKGATE_MASK(2) | + ANATOP_PFD_CLKGATE_MASK(3); + mask528 = ANATOP_PFD_CLKGATE_MASK(0) | + ANATOP_PFD_CLKGATE_MASK(1) | + ANATOP_PFD_CLKGATE_MASK(3); + + /* + * Don't reset PFD2 on DL/S + */ + if (is_6q) + mask528 |= ANATOP_PFD_CLKGATE_MASK(2); + writel(mask480, &anatop->pfd_480_set); + writel(mask528, &anatop->pfd_528_set); + writel(mask480, &anatop->pfd_480_clr); + writel(mask528, &anatop->pfd_528_clr); } #ifdef CONFIG_IMX_HDMI |