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| author | Ye.Li <B37916@freescale.com> | 2014-02-17 16:38:36 +0800 |
|---|---|---|
| committer | Nitin Garg <nitin.garg@freescale.com> | 2014-06-13 10:17:02 -0500 |
| commit | 0b02843b18d3a2c5c8012c4248a5574a8f6998c7 (patch) | |
| tree | 58d88f6a7910b3aa984a04413371ef192a997920 /arch/arm/cpu/armv7/mx6/soc.c | |
| parent | 2ead2f9501c6d2571e0f5365bd808ed7c73257ef (diff) | |
| download | u-boot-imx-0b02843b18d3a2c5c8012c4248a5574a8f6998c7.zip u-boot-imx-0b02843b18d3a2c5c8012c4248a5574a8f6998c7.tar.gz u-boot-imx-0b02843b18d3a2c5c8012c4248a5574a8f6998c7.tar.bz2 | |
ENGR00315499-20 ARM:imx6 Fix USDHC driver bug in PIO mode
When configure the USDHC driver to PIO mode by defining
"CONFIG_SYS_FSL_ESDHC_USE_PIO", the SD/MMC read and write will fail.
Two bugs in the driver to cause the issue:
1. The read buffer was invalidated after reading from DATAPORT register,
which should be only applied to DMA mode. The valid data in cache was
overwritten by physical memory.
2. The watermarks are not set in PIO mode, will cause according state not
be set.
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit e2ced39867a3001390bd23069e56b513ed268bb0)
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
Diffstat (limited to 'arch/arm/cpu/armv7/mx6/soc.c')
0 files changed, 0 insertions, 0 deletions