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| author | Wolfgang Denk <wd@denx.de> | 2013-10-04 17:43:24 +0200 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2013-10-14 16:06:54 -0400 |
| commit | 93e1459641e758d2b096d3f1b39414a39bb314f8 (patch) | |
| tree | 3780156a164d3924a2412354872203e4b46f8592 /arch/arm/cpu/armv7/mx5/lowlevel_init.S | |
| parent | 3765b3e7bd0f8e46914d417f29cbcb0c72b1acf7 (diff) | |
| download | u-boot-imx-93e1459641e758d2b096d3f1b39414a39bb314f8.zip u-boot-imx-93e1459641e758d2b096d3f1b39414a39bb314f8.tar.gz u-boot-imx-93e1459641e758d2b096d3f1b39414a39bb314f8.tar.bz2 | |
Coding Style cleanup: replace leading SPACEs by TABs
Signed-off-by: Wolfgang Denk <wd@denx.de>
[trini: Drop changes for PEP 4 following python tools]
Signed-off-by: Tom Rini <trini@ti.com>
Diffstat (limited to 'arch/arm/cpu/armv7/mx5/lowlevel_init.S')
| -rw-r--r-- | arch/arm/cpu/armv7/mx5/lowlevel_init.S | 44 |
1 files changed, 22 insertions, 22 deletions
diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S index fc7c767..25fadf6 100644 --- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S +++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S @@ -31,10 +31,10 @@ /* reconfigure L2 cache aux control reg */ ldr r0, =0xC0 | /* tag RAM */ \ - 0x4 | /* data RAM */ \ - 1 << 24 | /* disable write allocate delay */ \ - 1 << 23 | /* disable write allocate combine */ \ - 1 << 22 /* disable write allocate */ + 0x4 | /* data RAM */ \ + 1 << 24 | /* disable write allocate delay */ \ + 1 << 23 | /* disable write allocate combine */ \ + 1 << 22 /* disable write allocate */ #if defined(CONFIG_MX51) ldr r3, [r4, #ROM_SI_REV] @@ -290,20 +290,20 @@ setup_pll_func: setup_pll PLL1_BASE_ADDR, 800 - setup_pll PLL3_BASE_ADDR, 400 + setup_pll PLL3_BASE_ADDR, 400 - /* Switch peripheral to PLL3 */ - ldr r0, =CCM_BASE_ADDR - ldr r1, =0x00015154 - str r1, [r0, #CLKCTL_CBCMR] - ldr r1, =0x02898945 - str r1, [r0, #CLKCTL_CBCDR] - /* make sure change is effective */ + /* Switch peripheral to PLL3 */ + ldr r0, =CCM_BASE_ADDR + ldr r1, =0x00015154 + str r1, [r0, #CLKCTL_CBCMR] + ldr r1, =0x02898945 + str r1, [r0, #CLKCTL_CBCDR] + /* make sure change is effective */ 1: ldr r1, [r0, #CLKCTL_CDHIPR] - cmp r1, #0x0 - bne 1b + cmp r1, #0x0 + bne 1b - setup_pll PLL2_BASE_ADDR, 400 + setup_pll PLL2_BASE_ADDR, 400 /* Switch peripheral to PLL2 */ ldr r0, =CCM_BASE_ADDR @@ -324,7 +324,7 @@ setup_pll_func: cmp r1, #0x0 bne 1b - setup_pll PLL3_BASE_ADDR, 216 + setup_pll PLL3_BASE_ADDR, 216 setup_pll PLL4_BASE_ADDR, 455 @@ -358,13 +358,13 @@ setup_pll_func: str r1, [r0, #CLKCTL_CCGR6] str r1, [r0, #CLKCTL_CCGR7] - mov r1, #0x00000 - str r1, [r0, #CLKCTL_CCDR] + mov r1, #0x00000 + str r1, [r0, #CLKCTL_CCDR] - /* for cko - for ARM div by 8 */ - mov r1, #0x000A0000 - add r1, r1, #0x00000F0 - str r1, [r0, #CLKCTL_CCOSR] + /* for cko - for ARM div by 8 */ + mov r1, #0x000A0000 + add r1, r1, #0x00000F0 + str r1, [r0, #CLKCTL_CCOSR] #endif /* CONFIG_MX53 */ .endm |