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authorStefan Roese <sr@denx.de>2015-09-17 17:30:29 +0200
committerMarek Vasut <marex@denx.de>2015-09-23 03:53:36 +0200
commite1df080b0d8b1bf9ed3e6a01a647192b2c90c72a (patch)
tree332b9191cb14d44ccb5a455d70bd3afc266bdbb0 /arch/arm/cpu/armv7/ls102xa/cpu.c
parent8a5f6129d1450f5ff92a55cfcfd7b96ee019e303 (diff)
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arm: socfpga: Fix cache configuration
By not defining CONFIG_SYS_ARM_CACHE_WRITEALLOC, the WRITEBACK cache policy is selected. This leads to much better performance on the SoCFPGA. A quick network test shows this: Without this patch: => tftp 100000 big-40mb Speed: 1000, full duplex Using dwmac.ff702000 device TFTP from server 192.168.1.54; our IP address is 192.168.1.252 Filename 'big-40mb'. Load address: 0x100000 Loading: ################################################################# ################################################################# ################################################################# ################################################################# ########################## 2.5 MiB/s With this patch: => tftp 100000 big-40mb Speed: 1000, full duplex Using dwmac.ff702000 device TFTP from server 192.168.1.54; our IP address is 192.168.1.252 Filename 'big-40mb'. Load address: 0x100000 Loading: ################################################################# ################################################################# ################################################################# ################################################################# ########################## 7.6 MiB/s A performance improvement of factor ~3. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com> Cc: Pavel Machek <pavel@denx.de> Cc: Marek Vasut <marex@denx.de>
Diffstat (limited to 'arch/arm/cpu/armv7/ls102xa/cpu.c')
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