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authorJoonyoung Shim <jy0922.shim@samsung.com>2014-12-22 19:46:30 +0900
committerMinkyu Kang <mk7.kang@samsung.com>2014-12-24 10:56:24 +0900
commitfb56435f504b401e3a4e66fc98098f1de447c789 (patch)
treed189fc3409ef41889aa360350e9c730efcec7fd4 /arch/arm/cpu/armv7/exynos
parent68904c83226d8bd519d7937958df578b26719ce2 (diff)
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arm: exynos: clock: support SPLL as mmc source clock for exynos5420
MMC of exynos5420 can select SPLL as source clock, so add to support SPLL in exynos5420_get_mmc_clk(). It was tested on Odroid-XU3 board. Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Diffstat (limited to 'arch/arm/cpu/armv7/exynos')
-rw-r--r--arch/arm/cpu/armv7/exynos/clock.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
index 8fab135..b31c13b 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -848,6 +848,8 @@ static unsigned long exynos5420_get_mmc_clk(int dev_index)
if (sel == 0x3)
sclk = get_pll_clk(MPLL);
+ else if (sel == 0x4)
+ sclk = get_pll_clk(SPLL);
else if (sel == 0x6)
sclk = get_pll_clk(EPLL);
else