diff options
author | Chander Kashyap <chander.kashyap@linaro.org> | 2012-02-05 23:01:46 +0000 |
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committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2012-02-12 10:11:30 +0100 |
commit | 37bb6d89de399a6fc2aa0905452dd780e15e9900 (patch) | |
tree | 75b9654a40caa3fc170901da2b417bdd3d626b9f /arch/arm/cpu/armv7/exynos | |
parent | 5e46f83cc3569b95cef68dfd0722663260af91d0 (diff) | |
download | u-boot-imx-37bb6d89de399a6fc2aa0905452dd780e15e9900.zip u-boot-imx-37bb6d89de399a6fc2aa0905452dd780e15e9900.tar.gz u-boot-imx-37bb6d89de399a6fc2aa0905452dd780e15e9900.tar.bz2 |
ARM: EXYNOS: Add support for Exynos5 based SoCs
Samsung's ARM Cortex-A15 based SoCs are known as Exynos5 series of
SoCs. This patch adds the support for Exynos5.
Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Diffstat (limited to 'arch/arm/cpu/armv7/exynos')
-rw-r--r-- | arch/arm/cpu/armv7/exynos/clock.c | 208 |
1 files changed, 203 insertions, 5 deletions
diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 4d92c53..2f7048b 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -92,6 +92,72 @@ static unsigned long exynos4_get_pll_clk(int pllreg) return fout; } +/* exynos5: return pll clock frequency */ +static unsigned long exynos5_get_pll_clk(int pllreg) +{ + struct exynos5_clock *clk = + (struct exynos5_clock *)samsung_get_base_clock(); + unsigned long r, m, p, s, k = 0, mask, fout; + unsigned int freq; + + switch (pllreg) { + case APLL: + r = readl(&clk->apll_con0); + break; + case MPLL: + r = readl(&clk->mpll_con0); + break; + case EPLL: + r = readl(&clk->epll_con0); + k = readl(&clk->epll_con1); + break; + case VPLL: + r = readl(&clk->vpll_con0); + k = readl(&clk->vpll_con1); + break; + default: + printf("Unsupported PLL (%d)\n", pllreg); + return 0; + } + + /* + * APLL_CON: MIDV [25:16] + * MPLL_CON: MIDV [25:16] + * EPLL_CON: MIDV [24:16] + * VPLL_CON: MIDV [24:16] + */ + if (pllreg == APLL || pllreg == MPLL) + mask = 0x3ff; + else + mask = 0x1ff; + + m = (r >> 16) & mask; + + /* PDIV [13:8] */ + p = (r >> 8) & 0x3f; + /* SDIV [2:0] */ + s = r & 0x7; + + freq = CONFIG_SYS_CLK_FREQ; + + if (pllreg == EPLL) { + k = k & 0xffff; + /* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */ + fout = (m + k / 65536) * (freq / (p * (1 << s))); + } else if (pllreg == VPLL) { + k = k & 0xfff; + /* FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV) */ + fout = (m + k / 1024) * (freq / (p * (1 << s))); + } else { + if (s < 1) + s = 1; + /* FOUT = MDIV * FIN / (PDIV * 2^(SDIV - 1)) */ + fout = m * (freq / (p * (1 << (s - 1)))); + } + + return fout; +} + /* exynos4: return ARM clock frequency */ static unsigned long exynos4_get_arm_clk(void) { @@ -114,6 +180,28 @@ static unsigned long exynos4_get_arm_clk(void) return armclk; } +/* exynos5: return ARM clock frequency */ +static unsigned long exynos5_get_arm_clk(void) +{ + struct exynos5_clock *clk = + (struct exynos5_clock *)samsung_get_base_clock(); + unsigned long div; + unsigned long armclk; + unsigned int arm_ratio; + unsigned int arm2_ratio; + + div = readl(&clk->div_cpu0); + + /* ARM_RATIO: [2:0], ARM2_RATIO: [30:28] */ + arm_ratio = (div >> 0) & 0x7; + arm2_ratio = (div >> 28) & 0x7; + + armclk = get_pll_clk(APLL) / (arm_ratio + 1); + armclk /= (arm2_ratio + 1); + + return armclk; +} + /* exynos4: return pwm clock frequency */ static unsigned long exynos4_get_pwm_clk(void) { @@ -157,6 +245,27 @@ static unsigned long exynos4_get_pwm_clk(void) return pclk; } +/* exynos5: return pwm clock frequency */ +static unsigned long exynos5_get_pwm_clk(void) +{ + struct exynos5_clock *clk = + (struct exynos5_clock *)samsung_get_base_clock(); + unsigned long pclk, sclk; + unsigned int ratio; + + /* + * CLK_DIV_PERIC3 + * PWM_RATIO [3:0] + */ + ratio = readl(&clk->div_peric3); + ratio = ratio & 0xf; + sclk = get_pll_clk(MPLL); + + pclk = sclk / (ratio + 1); + + return pclk; +} + /* exynos4: return uart clock frequency */ static unsigned long exynos4_get_uart_clk(int dev_index) { @@ -204,6 +313,53 @@ static unsigned long exynos4_get_uart_clk(int dev_index) return uclk; } +/* exynos5: return uart clock frequency */ +static unsigned long exynos5_get_uart_clk(int dev_index) +{ + struct exynos5_clock *clk = + (struct exynos5_clock *)samsung_get_base_clock(); + unsigned long uclk, sclk; + unsigned int sel; + unsigned int ratio; + + /* + * CLK_SRC_PERIC0 + * UART0_SEL [3:0] + * UART1_SEL [7:4] + * UART2_SEL [8:11] + * UART3_SEL [12:15] + * UART4_SEL [16:19] + * UART5_SEL [23:20] + */ + sel = readl(&clk->src_peric0); + sel = (sel >> (dev_index << 2)) & 0xf; + + if (sel == 0x6) + sclk = get_pll_clk(MPLL); + else if (sel == 0x7) + sclk = get_pll_clk(EPLL); + else if (sel == 0x8) + sclk = get_pll_clk(VPLL); + else + return 0; + + /* + * CLK_DIV_PERIC0 + * UART0_RATIO [3:0] + * UART1_RATIO [7:4] + * UART2_RATIO [8:11] + * UART3_RATIO [12:15] + * UART4_RATIO [16:19] + * UART5_RATIO [23:20] + */ + ratio = readl(&clk->div_peric0); + ratio = (ratio >> (dev_index << 2)) & 0xf; + + uclk = sclk / (ratio + 1); + + return uclk; +} + /* exynos4: set the mmc clock */ static void exynos4_set_mmc_clk(int dev_index, unsigned int div) { @@ -231,27 +387,69 @@ static void exynos4_set_mmc_clk(int dev_index, unsigned int div) writel(val, addr); } +/* exynos5: set the mmc clock */ +static void exynos5_set_mmc_clk(int dev_index, unsigned int div) +{ + struct exynos5_clock *clk = + (struct exynos5_clock *)samsung_get_base_clock(); + unsigned int addr; + unsigned int val; + + /* + * CLK_DIV_FSYS1 + * MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24] + * CLK_DIV_FSYS2 + * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24] + */ + if (dev_index < 2) { + addr = (unsigned int)&clk->div_fsys1; + } else { + addr = (unsigned int)&clk->div_fsys2; + dev_index -= 2; + } + + val = readl(addr); + val &= ~(0xff << ((dev_index << 4) + 8)); + val |= (div & 0xff) << ((dev_index << 4) + 8); + writel(val, addr); +} + unsigned long get_pll_clk(int pllreg) { - return exynos4_get_pll_clk(pllreg); + if (cpu_is_exynos5()) + return exynos5_get_pll_clk(pllreg); + else + return exynos4_get_pll_clk(pllreg); } unsigned long get_arm_clk(void) { - return exynos4_get_arm_clk(); + if (cpu_is_exynos5()) + return exynos5_get_arm_clk(); + else + return exynos4_get_arm_clk(); } unsigned long get_pwm_clk(void) { - return exynos4_get_pwm_clk(); + if (cpu_is_exynos5()) + return exynos5_get_pwm_clk(); + else + return exynos4_get_pwm_clk(); } unsigned long get_uart_clk(int dev_index) { - return exynos4_get_uart_clk(dev_index); + if (cpu_is_exynos5()) + return exynos5_get_uart_clk(dev_index); + else + return exynos4_get_uart_clk(dev_index); } void set_mmc_clk(int dev_index, unsigned int div) { - exynos4_set_mmc_clk(dev_index, div); + if (cpu_is_exynos5()) + exynos5_set_mmc_clk(dev_index, div); + else + exynos4_set_mmc_clk(dev_index, div); } |