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author | Tom Rini <trini@ti.com> | 2013-04-15 07:46:11 -0400 |
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committer | Tom Rini <trini@ti.com> | 2013-04-15 07:46:11 -0400 |
commit | 17059f972fa6768ebf15a575c00083b3a431b79a (patch) | |
tree | 30df6b88fa1dc57dada54f9a16ab1619cc4f3c52 /arch/arm/cpu/armv7/exynos/soc.c | |
parent | 277f037074fbb73be10a7bff27079b6eb0a3bfbb (diff) | |
parent | 8960af8ba9488fc54e2e4733cbada26d3cece225 (diff) | |
download | u-boot-imx-17059f972fa6768ebf15a575c00083b3a431b79a.zip u-boot-imx-17059f972fa6768ebf15a575c00083b3a431b79a.tar.gz u-boot-imx-17059f972fa6768ebf15a575c00083b3a431b79a.tar.bz2 |
Merge branch 'master' of git://git.denx.de/u-boot-arm
Diffstat (limited to 'arch/arm/cpu/armv7/exynos/soc.c')
-rw-r--r-- | arch/arm/cpu/armv7/exynos/soc.c | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/exynos/soc.c b/arch/arm/cpu/armv7/exynos/soc.c index ab65b8d..e948e4c 100644 --- a/arch/arm/cpu/armv7/exynos/soc.c +++ b/arch/arm/cpu/armv7/exynos/soc.c @@ -23,6 +23,14 @@ #include <common.h> #include <asm/io.h> +#include <asm/system.h> + +enum l2_cache_params { + CACHE_TAG_RAM_SETUP = (1 << 9), + CACHE_DATA_RAM_SETUP = (1 << 5), + CACHE_TAG_RAM_LATENCY = (2 << 6), + CACHE_DATA_RAM_LATENCY = (2 << 0) +}; void reset_cpu(ulong addr) { @@ -36,3 +44,31 @@ void enable_caches(void) dcache_enable(); } #endif + +#ifndef CONFIG_SYS_L2CACHE_OFF +/* + * Set L2 cache parameters + */ +static void exynos5_set_l2cache_params(void) +{ + unsigned int val = 0; + + asm volatile("mrc p15, 1, %0, c9, c0, 2\n" : "=r"(val)); + + val |= CACHE_TAG_RAM_SETUP | + CACHE_DATA_RAM_SETUP | + CACHE_TAG_RAM_LATENCY | + CACHE_DATA_RAM_LATENCY; + + asm volatile("mcr p15, 1, %0, c9, c0, 2\n" : : "r"(val)); +} + +/* + * Sets L2 cache related parameters before enabling data cache + */ +void v7_outer_cache_enable(void) +{ + if (cpu_is_exynos5()) + exynos5_set_l2cache_params(); +} +#endif |