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author | Wolfgang Denk <wd@denx.de> | 2011-10-28 00:15:19 +0200 |
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committer | Wolfgang Denk <wd@denx.de> | 2011-10-28 00:15:19 +0200 |
commit | 87a5d601031652293ec4b729fdb7ee01bbd940a8 (patch) | |
tree | 91ede3ee45b228736c1876a700024782d7bc2032 /arch/arm/cpu/armv7/am33xx/ddr.c | |
parent | 606a76f8ef479e42ae4d06f8f3ce87e9a1c72acf (diff) | |
parent | 37fc0ed268dc5acacd3a83adafa26eb1a84e90af (diff) | |
download | u-boot-imx-87a5d601031652293ec4b729fdb7ee01bbd940a8.zip u-boot-imx-87a5d601031652293ec4b729fdb7ee01bbd940a8.tar.gz u-boot-imx-87a5d601031652293ec4b729fdb7ee01bbd940a8.tar.bz2 |
Merge branch 'master' of git://git.denx.de/u-boot-arm
* 'master' of git://git.denx.de/u-boot-arm:
ARM: Add Calxeda Highbank platform
dkb: make mmc command as default enabled
Marvell: dkb: add mmc support
ARM: pantheon: add mmc definition
davinci: remove config.mk file from the sources
ARM:AM33XX: Add support for TI AM335X EVM
ARM:AM33XX: Added timer support
ARM:AM33XX: Add emif/ddr support
ARM:AM33XX: Add clock definitions
ARM:AM33XX: Added support for AM33xx
omap3/emif4: fix registers definition
davinci: remove obsolete macro CONFIG_EMAC_MDIO_PHY_NUM
davinci: emac: add support for more than 1 PHYs
davinci: emac: add new features to autonegotiate for EMAC
da850evm: Move LPSC configuration to board_early_init_f()
omap4_panda: Build in cmd_gpio support on panda
omap: Don't use gpio_free to change direction to input
mmc: omap: Allow OMAP_HSMMC[23]_BASE to be unset
OMAP3: overo : Add environment variable optargs to bootargs
OMAP3: overo: Move ethernet CS4 configuration to execute based on board id
OMAP3: overo : Use ttyO2 instead of ttyS2.
da830: add support for NAND boot mode
dm36x: revert cache disable patch
dm644X: revert cache disable patch
devkit8000: Add malloc space
omap: spl: fix build break due to changes in FAT
OMAP3 SPL: Provide weak omap_rev_string
omap: beagle: Use ubifs instead of jffs2 for nand boot
omap: overo: Disable pull-ups on camera PCLK, HS and VS signals
omap: overo: Configure mux for gpio10
SPL: Add DMA library
omap3: Add interface for omap3 DMA
omap3: Add DMA register accessors
omap3: Add Base register for DMA
arm, davinci: add missing LSPC define for MMC/SD1
U-Boot/SPL: omap4: Make ddr pre-calculated timings as default.
DaVinci: correct MDSTAT.STATE mask
omap4: splitting padconfs into common, 4430 and 4460
omap4: adding revision detection for 4460 ES1.1
omap4: replacing OMAP4_CONTROL with OMAP4430_CONTROL
gplug: fixed build error as a result of code cleanup patch
kirkwood_spi: add dummy spi_init()
gpio: mvmfp: reduce include platform file
ARM: orion5x: reduce dependence of including platform file
serial: reduce include platform file for marvell chip
ARM: kirkwood: reduce dependence of including platform file
ARM: armada100: reduce dependence of including platform file
ARM: pantheon: reduce dependence of including platform file
Armada100: Add env storage support for Marvell gplugD
Armada100: Add SPI flash support for Marvell gplugD
Armada100: Add SPI support for Marvell gplugD
SPI: Add SPI driver support for Marvell Armada100
dreamplug: initial board support.
imx: fix coding style
misc: pmic: drop old Freescale's pmic driver
MX31: mx31pdk: use new pmic driver
MX31: mx31ads: use new pmic driver
MX31: mx31_litekit: use new pmic driver
MX5: mx53evk: use new pmic driver
MX5: mx51evk: use new pmic driver
MX35: mx35pdk: use new pmic driver
misc: pmic: addI2C support to pmic_fsl driver
misc: pmic: use I2C_SET_BUS in pmic I2C
MX5: efikamx/efikasb: use new pmic driver
MX3: qong: use new pmic driver
RTC: Switch mc13783 to generic pmic code
MX5: vision2: use new pmic driver
misc: pmic: Freescale PMIC switches to generic PMIC driver
misc:pmic:samsung Enable PMIC driver at GONI target
misc:pmic:max8998 MAX8998 support at a new PMIC driver.
misc:pmic:core New generic PMIC driver
mx31pdk: Remove unneeded config
mx31: provide readable WEIM CS accessor
MX51: vision2: Set global macros
I2C: Add i2c_get/set_speed() to mxc_i2c.c
ARM: Update mach-types
devkit8000: Add config to enable SPL MMC boot
devkit8000: protect board_mmc_init
arm, post: add missing post_time_ms for arm
cosmetic, post: Codingstyle cleanup
arm, logbuffer: make it compileclean
tegra2: Enable MMC for Seaboard
tegra2: Add more pinmux functions
tegra2: Rename PIN_ to PINGRP_
tegra2: Add more clock functions
tegra2: Clean up board code a little
tegra2: Rename CLOCK_PLL_ID to CLOCK_ID
Diffstat (limited to 'arch/arm/cpu/armv7/am33xx/ddr.c')
-rw-r--r-- | arch/arm/cpu/armv7/am33xx/ddr.c | 147 |
1 files changed, 147 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c new file mode 100644 index 0000000..ed982c1 --- /dev/null +++ b/arch/arm/cpu/armv7/am33xx/ddr.c @@ -0,0 +1,147 @@ +/* + * DDR Configuration for AM33xx devices. + * + * Copyright (C) 2011 Texas Instruments Incorporated - +http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed .as is. WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <asm/arch/cpu.h> +#include <asm/arch/ddr_defs.h> +#include <asm/io.h> + +/** + * Base address for EMIF instances + */ +static struct emif_regs *emif_reg = { + (struct emif_regs *)EMIF4_0_CFG_BASE}; + +/** + * Base address for DDR instance + */ +static struct ddr_regs *ddr_reg[2] = { + (struct ddr_regs *)DDR_PHY_BASE_ADDR, + (struct ddr_regs *)DDR_PHY_BASE_ADDR2}; + +/** + * Base address for ddr io control instances + */ +static struct ddr_cmdtctrl *ioctrl_reg = { + (struct ddr_cmdtctrl *)DDR_CONTROL_BASE_ADDR}; + +/** + * As a convention, all functions here return 0 on success + * -1 on failure. + */ + +/** + * Configure SDRAM + */ +int config_sdram(struct sdram_config *cfg) +{ + writel(cfg->sdrcr, &emif_reg->sdrcr); + writel(cfg->sdrcr2, &emif_reg->sdrcr2); + writel(cfg->refresh, &emif_reg->sdrrcr); + writel(cfg->refresh_sh, &emif_reg->sdrrcsr); + + return 0; +} + +/** + * Set SDRAM timings + */ +int set_sdram_timings(struct sdram_timing *t) +{ + writel(t->time1, &emif_reg->sdrtim1); + writel(t->time1_sh, &emif_reg->sdrtim1sr); + writel(t->time2, &emif_reg->sdrtim2); + writel(t->time2_sh, &emif_reg->sdrtim2sr); + writel(t->time3, &emif_reg->sdrtim3); + writel(t->time3_sh, &emif_reg->sdrtim3sr); + + return 0; +} + +/** + * Configure DDR PHY + */ +int config_ddr_phy(struct ddr_phy_control *p) +{ + writel(p->reg, &emif_reg->ddrphycr); + writel(p->reg_sh, &emif_reg->ddrphycsr); + + return 0; +} + +/** + * Configure DDR CMD control registers + */ +int config_cmd_ctrl(struct cmd_control *cmd) +{ + writel(cmd->cmd0csratio, &ddr_reg[0]->cm0csratio); + writel(cmd->cmd0csforce, &ddr_reg[0]->cm0csforce); + writel(cmd->cmd0csdelay, &ddr_reg[0]->cm0csdelay); + writel(cmd->cmd0dldiff, &ddr_reg[0]->cm0dldiff); + writel(cmd->cmd0iclkout, &ddr_reg[0]->cm0iclkout); + + writel(cmd->cmd1csratio, &ddr_reg[0]->cm1csratio); + writel(cmd->cmd1csforce, &ddr_reg[0]->cm1csforce); + writel(cmd->cmd1csdelay, &ddr_reg[0]->cm1csdelay); + writel(cmd->cmd1dldiff, &ddr_reg[0]->cm1dldiff); + writel(cmd->cmd1iclkout, &ddr_reg[0]->cm1iclkout); + + writel(cmd->cmd2csratio, &ddr_reg[0]->cm2csratio); + writel(cmd->cmd2csforce, &ddr_reg[0]->cm2csforce); + writel(cmd->cmd2csdelay, &ddr_reg[0]->cm2csdelay); + writel(cmd->cmd2dldiff, &ddr_reg[0]->cm2dldiff); + writel(cmd->cmd2iclkout, &ddr_reg[0]->cm2iclkout); + + return 0; +} + +/** + * Configure DDR DATA registers + */ +int config_ddr_data(int macrono, struct ddr_data *data) +{ + writel(data->datardsratio0, &ddr_reg[macrono]->dt0rdsratio0); + writel(data->datardsratio1, &ddr_reg[macrono]->dt0rdsratio1); + + writel(data->datawdsratio0, &ddr_reg[macrono]->dt0wdsratio0); + writel(data->datawdsratio1, &ddr_reg[macrono]->dt0wdsratio1); + + writel(data->datawiratio0, &ddr_reg[macrono]->dt0wiratio0); + writel(data->datawiratio1, &ddr_reg[macrono]->dt0wiratio1); + writel(data->datagiratio0, &ddr_reg[macrono]->dt0giratio0); + writel(data->datagiratio1, &ddr_reg[macrono]->dt0giratio1); + + writel(data->datafwsratio0, &ddr_reg[macrono]->dt0fwsratio0); + writel(data->datafwsratio1, &ddr_reg[macrono]->dt0fwsratio1); + + writel(data->datawrsratio0, &ddr_reg[macrono]->dt0wrsratio0); + writel(data->datawrsratio1, &ddr_reg[macrono]->dt0wrsratio1); + + writel(data->datadldiff0, &ddr_reg[macrono]->dt0dldiff0); + + return 0; +} + +int config_io_ctrl(struct ddr_ioctrl *ioctrl) +{ + writel(ioctrl->cmd1ctl, &ioctrl_reg->cm0ioctl); + writel(ioctrl->cmd2ctl, &ioctrl_reg->cm1ioctl); + writel(ioctrl->cmd3ctl, &ioctrl_reg->cm2ioctl); + writel(ioctrl->data1ctl, &ioctrl_reg->dt0ioctl); + writel(ioctrl->data2ctl, &ioctrl_reg->dt1ioctl); + + return 0; +} |