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authorAneesh V <aneesh@ti.com>2011-06-16 23:30:47 +0000
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2011-07-04 10:55:25 +0200
commit2c451f7831208741d0ff7ca6046cffcd9ee49def (patch)
treeec885d6ce9bc97eca3128e83e9af35c5b063ffe1 /arch/arm/cpu/armv7/Makefile
parent4c93da7c392737f2036130c240e2b4bea773d703 (diff)
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armv7: cache maintenance operations for armv7
- Add a framework for layered cache maintenance - separate out SOC specific outer cache maintenance from maintenance of caches known to CPU - Add generic ARMv7 cache maintenance operations that affect all caches known to ARMv7 CPUs. For instance in Cortex-A8 these opertions will affect both L1 and L2 caches. In Cortex-A9 these will affect only L1 cache - D-cache operations supported: - Invalidate entire D-cache - Invalidate D-cache range - Flush(clean & invalidate) entire D-cache - Flush D-cache range - I-cache operations supported: - Invalidate entire I-cache - Add maintenance functions for TLB, branch predictor array etc. - Enable -march=armv7-a so that armv7 assembly instructions can be used Signed-off-by: Aneesh V <aneesh@ti.com>
Diffstat (limited to 'arch/arm/cpu/armv7/Makefile')
-rw-r--r--arch/arm/cpu/armv7/Makefile2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index 8c0e915..299792a 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(CPU).o
START := start.o
-COBJS := cpu.o
+COBJS := cpu.o cache_v7.o
COBJS += syslib.o
SRCS := $(START:.o=.S) $(COBJS:.o=.c)