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| author | Vladimir Zapolskiy <vz@mleia.com> | 2015-07-06 07:22:11 +0300 |
|---|---|---|
| committer | Joe Hershberger <joe.hershberger@ni.com> | 2015-08-11 13:43:04 -0500 |
| commit | 1a791892dcb5904c8b208535704714b07802e0b8 (patch) | |
| tree | 9090fa848633e940a5de22ea836c602f74f83694 /arch/arm/cpu/arm926ejs | |
| parent | 23f5db0e26f0e6c25ba143e700b4812efdd5f941 (diff) | |
| download | u-boot-imx-1a791892dcb5904c8b208535704714b07802e0b8.zip u-boot-imx-1a791892dcb5904c8b208535704714b07802e0b8.tar.gz u-boot-imx-1a791892dcb5904c8b208535704714b07802e0b8.tar.bz2 | |
net: lpc32xx: add RMII phy mode support
LPC32xx MAC and clock control configuration requires some minor quirks
to deal with a phy connected by RMII.
It's worth to mention that the kernel and legacy BSP from NXP sets
SUPP_RESET_RMII == (1 << 11) bit, however the description of this bit is
missing in shared LPC32x0 User Manual UM10326 Rev. 3, July 22, 2011
and in LPC32x0 Draft User Mannual Rev. 00.27, November 20, 2008, also
in my tests an SMSC LAN8700 phy device connected over RMII seems to
work correctly without touching this bit.
Add support of RMII, if CONFIG_RMII is defined, this option is aligned
with a number of boards, which already define the same config value.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Tested-by: Sylvain Lemieux <slemieux@tycoint.com>
Diffstat (limited to 'arch/arm/cpu/arm926ejs')
| -rw-r--r-- | arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c index 5a453e3..9c8d655 100644 --- a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c +++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c @@ -45,7 +45,12 @@ void lpc32xx_mac_init(void) { /* Enable MAC interface */ writel(CLK_MAC_REG | CLK_MAC_SLAVE | CLK_MAC_MASTER - | CLK_MAC_MII, &clk->macclk_ctrl); +#if defined(CONFIG_RMII) + | CLK_MAC_RMII, +#else + | CLK_MAC_MII, +#endif + &clk->macclk_ctrl); } void lpc32xx_mlc_nand_init(void) |