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authorFabio Estevam <fabio.estevam@freescale.com>2013-05-03 04:37:13 +0000
committerStefano Babic <sbabic@denx.de>2013-05-05 17:08:47 +0200
commitfb7383a7a27a6ae2442b7f0db89831478192fd2d (patch)
tree2b8fff77b97276c5b93d580d8eae738e3683b75f /arch/arm/cpu/arm926ejs/mxs
parent39a538d9920f9422edbe339f00abe2eb7e038741 (diff)
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mxs: spl_mem_init: Change EMI port priority
FSL bootlets code set the PORT_PRIORITY_ORDER field of register HW_EMI_CTRL as 0x2, which means: PORT0231 = 0x02 Priority Order: AXI0, AHB2, AHB3, AHB1 Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Diffstat (limited to 'arch/arm/cpu/arm926ejs/mxs')
-rw-r--r--arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
index 5eacd36..41fb803 100644
--- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
@@ -287,7 +287,7 @@ static void mx23_mem_init(void)
early_delay(20000);
/* Adjust EMI port priority. */
- clrsetbits_le32(0x80020000, 0x1f << 16, 0x8);
+ clrsetbits_le32(0x80020000, 0x1f << 16, 0x2);
early_delay(20000);
setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 19);