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authorReinhard Meyer <u-boot@emk-elektronik.de>2010-08-09 13:25:37 +0200
committerReinhard Meyer <u-boot@emk-elektronik.de>2010-09-03 11:21:51 +0200
commite0cd44c3c1209c281d67b18372e584b143885303 (patch)
treecae3c2e06825899b2b8d0171f924f2aab30d0e7f /arch/arm/cpu/arm926ejs/at91
parent93dfcbe3c89f985ccf7e951506208f5ade21cb78 (diff)
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AT91: reset.c: fix comments, add option
Signed-off-by: Reinhard Meyer <u-boot@emk-elektronik.de>
Diffstat (limited to 'arch/arm/cpu/arm926ejs/at91')
-rw-r--r--arch/arm/cpu/arm926ejs/at91/reset.c21
1 files changed, 11 insertions, 10 deletions
diff --git a/arch/arm/cpu/arm926ejs/at91/reset.c b/arch/arm/cpu/arm926ejs/at91/reset.c
index 1b67e77..d2569d8 100644
--- a/arch/arm/cpu/arm926ejs/at91/reset.c
+++ b/arch/arm/cpu/arm926ejs/at91/reset.c
@@ -27,18 +27,19 @@
#include <asm/arch/at91_rstc.h>
#include <asm/arch/io.h>
-/*
- * Reset the cpu by setting up the watchdog timer and let him time out.
- */
+/* Reset the cpu by telling the reset controller to do so */
void reset_cpu(ulong ignored)
{
at91_rstc_t *rstc = (at91_rstc_t *) AT91_RSTC_BASE;
- /* this is the way Linux does it */
-
- writel(AT91_RSTC_KEY | AT91_RSTC_CR_PROCRST | AT91_RSTC_CR_PERRST,
- &rstc->cr);
-
- while (1);
- /* Never reached */
+ writel(AT91_RSTC_KEY
+ | AT91_RSTC_CR_PROCRST /* Processor Reset */
+ | AT91_RSTC_CR_PERRST /* Peripheral Reset */
+#ifdef CONFIG_AT91RESET_EXTRST
+ | AT91_RSTC_CR_EXTRST /* External Reset (assert nRST pin) */
+#endif
+ , &rstc->cr);
+ /* never reached */
+ while (1)
+ ;
}